Method and circuit for the digital deflection correction of TV picture tubes

Claim 3

A method in accordance with claim 1, comprising the steps of: generating said horizontal deflection signals by with a triggerable horizontal oscillator providing trigger signals to said horizontal oscillator by delaying a horizontal synchronizing pulse by at least the period of time corresponding to a maximum east-west distortion of said picture tube storing said first digital video signals in a memory at a first frequency; reading said first digital video signals from said memory at said first frequency correcting by interpolation said first digital video signals read from said memory to provide said digital signals.

Claim 4

A method in accordance with claim 1 comprising the steps of: storing said first digital video signals in a memory at a first frequency reading said first digital video signals from said memory at a second frequency which is higher than said first frequency in accordance with a correction value to produce said digital video signals.

Claim 5

A circuit for digital deflection correction of television picture tubes which are controlled via digital-to-analog converters by digital video signals derived from composite color signals and in which a horizontal and vertical oscillators are triggered by a horizontal and vertical sync pulses to produce sawtooth deflection signals for horizontal and vertical deflection purposes, respectively, said circuit comprising: a delay stage receiving said horizontal sync pulse and delaying application of said horizontal sync pulse to said horizontal oscillator by a time delay at least equal to the maximum east-west deflection distortion; a memory, addressable via write and read addresses for storing said digital signals; a write address generator coupled to said memory, said write address generator being clocked by first clock signals at a first predetermined rate; a read address generator coupled to said memory, said read address generator being clocked by second clock signals at a second predetermined rate, said second predetermined rate being higher than said first predetermined rate; and said read address generator comprising: a digital horizontal parabola generator resettable by said horizontal sync pulse, a first read only memory containing three first coefficients determinative of the horizontal center-of-screen parabola and their vertical direction dependent first correction values, a digital vertical parabola generator resettable by said vertical sync pulse, a second read only memory containing three second coefficients determinative of the vertical center of screen parabola and their horizontal direction dependent second correction values.

Claim 6

A circuit for digital deflection correction of television picture tubes which are controlled via digital-to-analog converters by digital video signals derived from composite color signals and in which a horizontal and vertical oscillators are triggered by a horizontal and vertical sync pulses to produce sawtooth deflection signals for horizontal and vertical deflection purposes, respectively, said circuit comprising: a delay stage receiving said horizontal sync pulse and delaying application of said horizontal sync pulse to said horizontal oscillator by a time delay at least equal to the maximum east-west deflection distortion; a memory, addressable via write and read addresses for storing said digital signals; a write address generator coupled to said memory, said write address generator being clocked by first clock signals at a first predetermined rate; a read address generator coupled to said memory, said read address generator being clocked by second clock signals at a second predetermined rate, said second predetermined rate being higher than said first predetermined rate; and said read address generator comprising: a digital horizontal parabola generator resettable by said horizontal sync pulse, a first read only memory containing three first coefficients determinative of the horizontal center-of-screen parabola and their vertical direction dependent first correction values, a digital vertical parabola generator resettable by said vertical sync pulse, a second read only memory containing three second coefficients determinative of the vertical center of screen parabola and their horizontal direction dependent second correction values.

Claim 7

A circuit in accordance with claim 4 comprising: a non-integer frequency multiplier for producing said second clock signals from said first clock signals, the non-integer factor of said multiplier being in proportion to the digits of said read address generator exceeding the number of address digits on the low order side.

Claim 8

A circuit in accordance with claim 5 wherein said multiplier comprises: an integer frequency multiplier and a subsequently arranged frequency divider.

Claim 9

A circuit in accordance with claim 4 wherein: at least one of said vertical or horizontal parabola generators comprises: a first summer having one input receiving a respective one of said first or second coefficients, and having a second input coupled to its output via a first delay line register preloaded with a second one of said first or second coefficients; a second summer having one input coupled to said first summer output, a second input coupled to its output via a second delay line register preloaded with a third one of said first or second coefficients; and the delay time of said first and second delay line registers each being equal to the period of said first clock signals.

Claim 10

A circuit for digital deflection correction of television picture tubes which are controlled via digital-to-analog converters by digital video signals derived from composite color signals and digitally reconditioned by a video processor, and in which horizontal and vertical oscillators are triggered by horizontal and vertical synch pulses to produce sawtooth deflection purposes, respectively, said circuit comprising: a delay stage receiving said horizontal synch pulse and delaying application of said horizontal synch pulse to said horizontal oscillator by a time delay at least equal to the maximum east-west deflection distortion; a memory having data inputs receiving said reconditioned signals and addressable via write and read addresses for storing said reconditioned signals; a write address generator coupled to said memory, said write address generator being clocked at a first predetermined rate and reset by said horizontal synch pulse; a read address generator coupled to said memory, said read address generator being clocked at said first predetermined rate synchronously with said write address generator and reset by the output of said delay stage; said read address generator comprising: a digital horizontal parabola generator resettable by said horizontal synch pulse, a digital vertical parabola generator resettable by said vertical synch pulse, a first read only memory for first coefficients determinative of the horizontal center-of-screen parabola and for vertical direction dependent first correction values, a second read only memory for second coefficients determinative of the vertical center-of-screen parabola and for horizontal direction dependent second correction values; an n th grade interpolator coupled to the output of said memory, where n is a non zero integer, and the interpolator performance characteristic thereof is determined from the read address generator digits which exceed an address positional number on the low order side, the output of said interpolator providing digital signals to said digital-to-analog converters; said memory in response to a read address providing an associated stored value and stored values associated with n following addresses simultaneously to said interpolator over n+1 parallel buses.

Claim 11

A circuit for digital deflection correction of television picture tubes which are controlled via digital-to-analog converters by digital video signals derived from composite color signals and digitally reconditioned by a video processor, and in which horizontal and vertical oscillators are triggered by horizontal and vertical synch pulses to produce sawtooth deflection purposes, respectively, said circuit comprising: a delay stage receiving said horizontal synch pulse and delaying application of said horizontal synch pulse to said horizontal oscillator by a time delay at least equal to the maximum east-west deflection distortion; a memory having data inputs receiving said reconditioned signals and addressable via write and read addresses for storing said reconditioned signals; a write address generator coupled to said memory, said write address generator being clocked at a first predetermined rate and reset by said horizontal synch pulse; a read address generator coupled to said memory, said read address generator being clocked at said first predetermined rate synchronously with said write address generator and reset by the output of said delay stage; said read address generator comprising: a digital horizontal parabola generator resettable by said horizontal synch pulse, a digital vertical parabola generator resettable by said vertical synch pulse, a first read only memory for first coefficients determinative of the horizontal center-of-screen parabola and for vertical direction dependent first correction values, a second read only memory for second coefficients determinative of the vertical center-of-screen parabola and for horizontal direction dependent second correction values; an n th grade interpolator coupled to the output of said memory, where n is a non zero integer, and the interpolator performance characteristic thereof is determined from the read address generator digits which exceed an address positional number on the low order side, the output of said interpolator providing digital signals to said digital-to-analog converters; said memory in response to a read address providing an associated stored value and stored values associated with n following addresses simultaneously to said interpolator over n+1 parallel buses.

Claim 12

A circuit in accordance with claim 8 wherein: said interpolation is of the first order, n=1, and comprises: a first multiplier having a first input coupled to the output of said memory for a first storage value via a first one of said buses, and a second input receiving the low order digits of said read address generator output; a second multiplier having a first input coupled to the ouput of said memory for the second storage value via a second one of said buses; an adder having first input coupled to said first multiplier output, a second input coupled to said second multiplier output; and a subtracter having a minuend input receiving a digital representation of the number one, a subtrahend input receiving said low order digits of said read address generator output, an output connected to the second input of said second multiplier.