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US4689504A Expired / Lapsed US ⏱️ 0.0 years remaining

High voltage decoder

Assignee: Motorola Solutions Inc
•
Filing: 1985-12-20
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Granted: 1987-08-25
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Expires: 2005-12-20
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Abstract

Abstract A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.

Inventors

  • 👤 Kuppuswamy Raghunathan
  • 👤 Jeffrey R. Jorvig
  • 👤 Stephen L. Smith

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 370 words
The high voltage CMOS decoder and level translator, comprising: a first N-channel field effect transistor having a source electrode for coupling to a first source of supply voltage, a gate electrode for receiving an input signal capable of assuming first and second stable states and having a drain electrode; a second N-channel field effect transistor having a source electrode for coupling to said first source of supply voltage, a gate electrode coupled to the complement of said input signal and having a drain electrode; a first P-channel field effect transistor having a source electrode for coupling to a second source of supply voltage higher than said first source of supply voltage and having gate and drain electrodes; a second P-channel field effect transistor having a source electrode for coupling to said second source of supply voltage and having gate and drain electrodes; a third N-channel field effect transistor having a source electrode coupled to the drain electrode of said first N-channel field effect transistor, a gate electrode for coupling to a third source of supply voltage intermediate said first and second sources of supply voltage and having a drain electrode; a third P-channel field effect transistor having a source electrode coupled to the drain electrode of said first P-channel field effect transistor, a drain electrode coupled to the drain electrode of said third N-channel field effect transistor and to the gate of said second P-channel field effect transistor to thereby provide an output node for said input signal, and a gate electrode coupled to a fourth source of supply voltage intermediate said first and second sources of supply voltage; a fourth N-channel field effect transistor having a source electrode coupled to the drain electrode of said second N-channel field effect transistor, a gate electrode for coupling to said third source of supply voltage and having a drain electrode; and a fourth P-channel field effect transistor having a source electrode coupled to the drain electrode of said second P-channel field effect transistor, a drain electrode coupled to the drain electrode of said fourth N-channel field effect transistor and to the gate electrode of said first P-channel field effect transistor, and a gate electrode coupled to said fourth source of supply voltage.
Claim 2
Dependent Claim 370 words
The high voltage CMOS decoder and level translator, comprising: a first N-channel field effect transistor having a source electrode for coupling to a first source of supply voltage, a gate electrode for receiving an input signal capable of assuming first and second stable states and having a drain electrode; a second N-channel field effect transistor having a source electrode for coupling to said first source of supply voltage, a gate electrode coupled to the complement of said input signal and having a drain electrode; a first P-channel field effect transistor having a source electrode for coupling to a second source of supply voltage higher than said first source of supply voltage and having gate and drain electrodes; a second P-channel field effect transistor having a source electrode for coupling to said second source of supply voltage and having gate and drain electrodes; a third N-channel field effect transistor having a source electrode coupled to the drain electrode of said first N-channel field effect transistor, a gate electrode for coupling to a third source of supply voltage intermediate said first and second sources of supply voltage and having a drain electrode; a third P-channel field effect transistor having a source electrode coupled to the drain electrode of said first P-channel field effect transistor, a drain electrode coupled to the drain electrode of said third N-channel field effect transistor and to the gate of said second P-channel field effect transistor to thereby provide an output node for said input signal, and a gate electrode coupled to a fourth source of supply voltage intermediate said first and second sources of supply voltage; a fourth N-channel field effect transistor having a source electrode coupled to the drain electrode of said second N-channel field effect transistor, a gate electrode for coupling to said third source of supply voltage and having a drain electrode; and a fourth P-channel field effect transistor having a source electrode coupled to the drain electrode of said second P-channel field effect transistor, a drain electrode coupled to the drain electrode of said fourth N-channel field effect transistor and to the gate electrode of said first P-channel field effect transistor, and a gate electrode coupled to said fourth source of supply voltage.
Claim 3
Dependent Claim 170 words
A circuit according to claim 1 further comprising: a fifth N-channel field effect transistor having a source electrode for coupling to a fifth source of supply current, a gate electrode coupled to said output node and having a drain electrode; a fifth P-channel field effect transistor having a source electrode for coupling to said second source of supply voltage, a gate electrode coupled to the drain electrode of said third N-channel field effect transistor and having a drain electrode; a sixth N-channel field effect transistor having a source electrode coupled to the drain electrode of said fifth N-channel field effect transistor, a gate electrode for coupling to said third source of supply voltage and having a drain electrode; and a sixth P-channel field effect transistor having a source electrode coupled to the drain electrode of said fifth P-channel field effect transistor, a drain electrode coupled to the drain electrode of said sixth N-channel field effect transistor and having a gate electrode for coupling to said fourth source of supply voltage.
Claim 4
Dependent Claim 23 words
A circuit according to claim 2 wherein said circuit has an output taken from the drain of said sixth P-channel field effect transistor.
Claim 5
Dependent Claim 27 words
A circuit according to claim 3 wherein said first source of supply voltage is approximately ground and said second source of supply voltage is approximately 20 volts.
Claim 6
Dependent Claim 19 words
A circuit according to claim 4 wherein said fourth and fifth sources of supply voltage are approximately 10 volts.

References Cited (Backward Citations)

US3942043A Cited
US4468576A Cited
US4508978A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-08-24 1991-02-23 1991-08-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-08-24 1995-02-23 1995-08-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-08-24 1999-02-23 1999-08-25 $7700.00 Window Closed / Lapsed

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