Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
In a data processing system comprising a central processor, a common data bus connected to said central processor, a plurality of controllers connected to said common bus, each controller respectively interfacing between said central processor and at least one storage unit or input/output device, means in said central processor for including in addresses sent on said common bus, identifier segments indicating the respective controller to which address is being sent, and programmable comparison means in each controller for comparing said identifier segment to a stored controller identifier representing said controller, the improvement comprising: a read-only initialization program stored in one of said storage units, said controller interfacing with said one storage unit being a master controller, means in said master controller selectively activated during initialization for accepting all addresses irrespective of the identifier segment, and means in each of said other controllers selectively activated during initialization, for disabling the programmable comparison means in each whereby no addresses are accepted by said other controllers.
Claim 2
Dependent Claim
163 words
In a data processing system comprising a central processor, a common data bus connected to said central processor, a plurality of controllers connected to said common bus, each controller respectively interfacing between said central processor and at least one storage unit or input/output device, means in said central processor for including in addresses sent on said common bus, identifier segments indicating the respective controller to which address is being sent, and programmable comparison means in each controller for comparing said identifier segment to a stored controller identifier representing said controller, the improvement comprising: a read-only initialization program stored in one of said storage units, said controller interfacing with said one storage unit being a master controller, means in said master controller selectively activated during initialization for accepting all addresses irrespective of the identifier segment, and means in each of said other controllers selectively activated during initialization, for disabling the programmable comparison means in each whereby no addresses are accepted by said other controllers.
Claim 3
Dependent Claim
40 words
The data processing system of claim 1 wherein said initialization program includes the controller identifiers representing each of said controllers, and said processor comprises means for applying to the comparison means in each controller the controller identifier representing said controller.
Claim 4
Dependent Claim
25 words
The data processing system of claim 1 wherein said means in said master controller for accepting all addresses includes means for by-passing said comparison means.
Claim 5
Dependent Claim
23 words
The data processing system of claim 1 wherein said read-only initialization program is stored in a read-only portion of said one storage unit.
Claim 6
Dependent Claim
58 words
The data processing system of claim 1 further including means for activating said accepting means in said master controller and said disabling means in said other controllers when said data processing system is powered on and deactivating said accepting means in said master controller and said disabling means in said other controllers upon completion of said initialization program.
Claim 7
Dependent Claim
125 words
The data processing system of claim 1 wherein said central processor comprises addressing means including an address space representing the range of storage addresses of storage locations which the processor is capable of accessing, and pointer means for pointing to the address of the storage location being accessed, said address space being subdivided into a plurality of repetitive address subspaces of equal size, all of the addresses in each subspace respectively having a common identifier segment, the range of addresses in each subspace being the same as the range in every other subspace except for the identifier segment whereby during initialization the master controller accesses the same location in said one storage unit in response to each of corresponding addresses in each of said subspaces.
Claim 8
Dependent Claim
77 words
The data processing system of claim 6 wherein said central processor further includes means responsive to powering-on of said processor for causing said pointer means to indicate a predetermined address in said address space for activating said accepting means in said master controller and said disabling means in said other controllers, said predetermined address having an identifier segment different than that of the address of the storage location accessed by pointing to said predetermined address during initialization.
Claim 9
Dependent Claim
57 words
The data processing system of claim 7 further including means for activating said accepting means in said master controller and said disabling means in said other controllers when said data processing system is powered on and deactivating accepting means in said master controller and said disabling means in said other controllers upon completion of said initialization program.
Claim 10
Dependent Claim
76 words
The data processing system of claim 8 wherein the storage location accessed by said predetermined address causes said pointer means to point to a subsequent address, said processor further including means to cause said pointer to point to an address having an identifier segment corresponding to the identifier segment in the address of the storage location being accessed before said accepting means in said master controller and said disabling means in said other controllers are deactivated.