US4687989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS powerless rom code mask option select
Assignee: STMicroelectronics lnc USA
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Filing: 1984-11-01
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Granted: 1987-08-18
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Expires: 2004-11-01
Abstract
Abstract An integrated circuit having an option between two or more configurations and also using a patterned ion-implant for impressing data (such as a ROM section of the circuit) may advantageously perform the option-specification simultaneously with the ROM; using a powerless option-specifying circuit permits testing portions of the circuit before the implantation step.
Inventors
- 👤 Harold L. Davis
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:01
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G06; G06F; G06F11/00; G06F11/006; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
177 words
A testable CMDS integrated circuit for specifying a circuit parameter by maintaining a preselected option node at a predetermined static voltage, comprising: a semiconductor substrate having an electrical circuit formed therein, said electrical circuit having at least one option node for forcing a subcircuit of said electrical circuit into a predetermined state dependent on a voltage at said option node; a P-channel transistor connected between a power supply voltage terminal and said option node; an N-channel transistor connected between said option node and ground; a gate node common to both of said P-channel and N-channel transistors; and voltage means connected to said gate node for supplying a steady-state voltage to said gate node; characterized in that: said voltage means comprises a resistive element, having a predetermined resistance, connected between said gate node and a current supply terminal; said circuit further comprises a test pin, exposed outside any covering layers of said integrated circuit and connected directly to said gate node, whereby voltage supplied to said test pin may override said voltage means to control said gate node.
Claim 2
Dependent Claim
177 words
A testable CMDS integrated circuit for specifying a circuit parameter by maintaining a preselected option node at a predetermined static voltage, comprising: a semiconductor substrate having an electrical circuit formed therein, said electrical circuit having at least one option node for forcing a subcircuit of said electrical circuit into a predetermined state dependent on a voltage at said option node; a P-channel transistor connected between a power supply voltage terminal and said option node; an N-channel transistor connected between said option node and ground; a gate node common to both of said P-channel and N-channel transistors; and voltage means connected to said gate node for supplying a steady-state voltage to said gate node; characterized in that: said voltage means comprises a resistive element, having a predetermined resistance, connected between said gate node and a current supply terminal; said circuit further comprises a test pin, exposed outside any covering layers of said integrated circuit and connected directly to said gate node, whereby voltage supplied to said test pin may override said voltage means to control said gate node.
Claim 3
Dependent Claim
27 words
An integrated circuit according to claim 1, further characterized in that said current supply terminal is a power supply terminal and the two transistors form an inverter.
Claim 4
Dependent Claim
43 words
An integrated circuit according to claim 1, further characterized in that a capacitor having a predetermined capacitance is connected between said gate node and ground, whereby said predetermined static voltage on said option node is insulated from voltage fluctuations on said gate node.
Claim 5
Dependent Claim
61 words
An integrated circuit according to claim 1, further characterized in that said gate node has a trip point voltage separating first and second voltage ranges controlling first and second voltage states of said option node respectively in which said trip point voltage is above said steady-state voltage on said gate node, whereby said option node is in said first voltage state.
Claim 6
Dependent Claim
61 words
An integrated circuit according to claim 1, further characterized in that said gate node has a trip point voltage separating first and second voltage ranges controlling first and second voltage states of said option node respectively in which said trip point voltage is below said steady-state voltage on said gate node, whereby said option node is in said second voltage state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-17 | 1991-02-16 | 1991-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-17 | 1995-02-16 | 1995-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-17 | 1999-02-16 | 1999-08-18 | $7700.00 | Window Closed / Lapsed |