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US4687955A Expired / Lapsed US ⏱️ 0.0 years remaining

Schmitt circuit with MIS field effect transistors

Assignee: Toshiba Corp
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Filing: 1986-09-26
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Granted: 1987-08-18
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Expires: 2006-09-26
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Abstract

Abstract This invention provides a Schmitt circuit comprising: a first transistor of depletion type, in which the drain is connected to a first power source and the gate and the source are connected to each other; second and third transistors of enhancement type are connected in series between the node where the gate and the source of the first transistor are connected together and a second power source, and the gates of the second and third transistors are connected to each other; a fourth transistor of enhancement type, in which the drain is connected to the first power source and the gate is connected to the node where the gate and source of the first transistor are connected together; a fifth transistor of depletion type, in which the drain is connected to the source of the fourth transistor and the gate and the source are connected together and are connected to the node where the source of the second transistor and the drain of the third transistor are connected together; an input terminal inputted an input signal at the node where the gates of the second and third transistors are connected together; and an outut terminal outputting an output signal from the node where the gate and source of the first transistor are connected together.

Inventors

  • 👤 Hiroyuki Koinuma

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 22:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/17; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 211 words
A Schmitt circuit comprising: a first transistor of depletion type, in which the drain is connected to a first power source and the gate and the source are connected to each other; second and third transistors of enhancement type are connected in series between the node where the gate and the source of the first transistor are connected together and a second power source, and the gates of the second and third transistors are connected to each other; a fourth transistor of enhancement type, in which the drain is connected to the first power source and the gate is connected to the node where the gate and source of the first transistor are connected together; a fifth transistor of depletion type, in which the drain is connected to the source of the fourth transistor and the gate and the source are connected together and are connected to the node where the source of the second transistor and the drain of the third transistor are connected together; an input terminal inputted an input signal at the node where the gates of the second and third transistors are connected together; and an output terminal outputting an output signal from the node where the gate and source of the first transistor are connected together.
Claim 2
Dependent Claim 211 words
A Schmitt circuit comprising: a first transistor of depletion type, in which the drain is connected to a first power source and the gate and the source are connected to each other; second and third transistors of enhancement type are connected in series between the node where the gate and the source of the first transistor are connected together and a second power source, and the gates of the second and third transistors are connected to each other; a fourth transistor of enhancement type, in which the drain is connected to the first power source and the gate is connected to the node where the gate and source of the first transistor are connected together; a fifth transistor of depletion type, in which the drain is connected to the source of the fourth transistor and the gate and the source are connected together and are connected to the node where the source of the second transistor and the drain of the third transistor are connected together; an input terminal inputted an input signal at the node where the gates of the second and third transistors are connected together; and an output terminal outputting an output signal from the node where the gate and source of the first transistor are connected together.
Claim 3
Dependent Claim 23 words
A Schmitt circuit according to claim 1, wherein the Schmitt circuit is used as an external signal input circuit in semiconductor integrated circuits.
Claim 4
Dependent Claim 38 words
A Schmitt circuit according to claim 1, wherein each of the transistors is N channel type, the first power source is of a higher potential than the second power source and the second power source is earth potential.
Claim 5
Dependent Claim 36 words
A Schmitt circuit according to claim 1, wherein the first transistor, in which the drain is connected to a third power source and the drain of the fourth transistor is connected to the first power source.
Claim 6
Dependent Claim 66 words
A Schmitt circuit according to claim 1, wherein the Schmitt circuit further comprises a sixth transistor of enhancement type, in which the drain is connected to the first power source, the gate is connected to the node where the gate and source of the first transistor are connected together, and the source is connected to the node where the second and third transistor are connected together.

References Cited (Backward Citations)

US4475048A Cited
US4506168A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-08-17 1991-02-16 1991-08-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-08-17 1995-02-16 1995-08-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-08-17 1999-02-16 1999-08-18 $7700.00 Window Closed / Lapsed

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