Low capacitance amorphous silicon field effect transistor structure

Claim 1

An amorphous silicon thin film field effect transistor, particularly for use in liquid crystal display devices, said field effect transistor comprising: an insulating substrate; a gate electrode disposed on said insulating substrate; an insulating layer disposed over said gate electrode; an amorphous silicon layer disposed over said insulating layer, said amorphous silicon layer possessing a thickness t; a drain electrode disposed on said amorphous silicon layer so as to partially overlie said gate electrode; a source electrode disposed on said amorphous silicon layer so as to define a channel region of length L in said amorphous silicon layer, said channel region extending in said amorphous silicon layer between said source electrode and said drain electrode, said source electrode overlying said gate electrode by a distance d; said distance d being given approximately by cμ e /(2Lα), where c is the gate capacitance per unit area, μ e is the effective electron mobility in the amorphous silicon layer and α is the ratio between current density J in the direction from the gate electrode to the source electrode in the region of their overlap and the gate voltage raised to the power 2.