Patent US4686483A successfully refreshed from Google Patents.
US4686483A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital filter circuit
Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1986-01-30
•
Granted: 1987-08-11
•
Expires: 2006-01-30
Abstract
Abstract A digital filter circuit includes first and second counters which set and reset a latch circuit at predetermined counts. Clock pulses and the input signal are passed through a gate circuit to the first counter which outputs a set signal to the latch circuit only if the input signal is maintained at a high level for the predetermined count. Clock pulses and the inverted input signal are passed through a gate circuit to the second counter which outputs a reset signal to the latch circuit only if the input signal is maintained at a low level for the predetermined count. In this manner noise pulses on the input signal are filtered out of the output signal obtained from the latch circuit.
Inventors
- 👤 Isao Isshiki
- 👤 Shinichiro Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:52
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/05; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
238 words
A digital filter circuit, for filtering noise from a bilevel input signal, said circuit comprising: clock means for generating a clock signal; first gate means for receiving said input signal and said clock signal and for outputting said clock signal when said input signal is at a high level; first counter means for receiving the output of said first gate means as a clock input, for providing a first output signal at a predetermined count of said clock input, but said first counter means being reset anytime from noise by said going to a low level; latching means being set in response to said first output signal of said first counter means; inverting means for receiving said input signal and generating an inverted input signal; second gate means for receiving said inverted input signal and said clock signal and for outputting said clock signal when said input signal is at a low level; second counter means for receiving the output of said second gate means as a clock input, and for providing a second output signal at a predetermined count of said clock input but, said second counter means being reset anytime from noise by said input signal going to a high level; said latching means being reset in response to said second output signal of said second counter means, whereby said latching means provides a filtered signal from the predetermined counts of said first and second counters.
Claim 2
Dependent Claim
238 words
A digital filter circuit, for filtering noise from a bilevel input signal, said circuit comprising: clock means for generating a clock signal; first gate means for receiving said input signal and said clock signal and for outputting said clock signal when said input signal is at a high level; first counter means for receiving the output of said first gate means as a clock input, for providing a first output signal at a predetermined count of said clock input, but said first counter means being reset anytime from noise by said going to a low level; latching means being set in response to said first output signal of said first counter means; inverting means for receiving said input signal and generating an inverted input signal; second gate means for receiving said inverted input signal and said clock signal and for outputting said clock signal when said input signal is at a low level; second counter means for receiving the output of said second gate means as a clock input, and for providing a second output signal at a predetermined count of said clock input but, said second counter means being reset anytime from noise by said input signal going to a high level; said latching means being reset in response to said second output signal of said second counter means, whereby said latching means provides a filtered signal from the predetermined counts of said first and second counters.
Claim 3
Dependent Claim
21 words
A circuit as claimed in claim 1 wherein said first and second gate means comprise first and second AND gates, respectively.
Claim 4
Dependent Claim
37 words
A circuit as claimed in claim 1 wherein said inverting means further provides said inverted input signal to said first counting means for resetting said first counting means whenever said input signal goes to a low level.
Claim 5
Dependent Claim
21 words
A circuit as claimed in claim 1 wherein said first and second gate means comprise first and second NAND gates, respectively.
Claim 6
Dependent Claim
114 words
A circuit as claimed in claim 1 wherein said first counting means comprises first and second flip-flops and a NOR gate; said first flip-flop receiving said output clock signal from said first gate means, having a first output connected to the input of said second flip-flop, having a second inverted output connected to a first input of said NOR gate and being reset by said input signal going to a low level; said second flip-flop having an inverted output connected to a second input of said NOR gate and being reset by said input signal going to a low level; the output of said NOR gate providing a latching signal to said latching means.
Claim 7
Dependent Claim
95 words
A circuit as claimed in claim 5 wherein said second counting means comprises third and fourth flip-flops and a third gate means; said third flip-flop receiving said output clock signal from said second gate means, having an output connected to the input of said fourth flip-flop and a first input of said third gate means and being reset by said input signal going to a high level; said fourth flip-flop having an output connected to a second input of said third gate means and being reset by said input signal going to a high level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |