Patent US4685076A successfully refreshed from Google Patents.
US4685076A
Expired / Lapsed
US
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Vector processor for processing one vector instruction with a plurality of vector processing units
Assignee: Hitachi Ltd
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Filing: 1984-10-03
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Granted: 1987-08-04
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Expires: 2004-10-03
Abstract
Abstract A vector processing apparatus comprises plural vector registers, plural vector arithmetic units, and data transfer circuits. The vector processing apparatus comprises plural vector processing units each having plural vector registers, at least one vector arithmetic unit and at least one data transfer circuit to designate the number of vector elements to be processed for each vector processing unit in executing one vector instruction, thereby carrying out the vector processings corresponding to the number of elements to be essentially processed as a whole.
Inventors
- 👤 Yaoko Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:52
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
A vector processing system comprising: main storage means for storing vector instructions and vector data; a plurality of vector processing units connected to said main storage means for processing different vector elements, each of the vector processing units including: (1) a plurality of vector registers; (2) at least one vector arithmetic unit, selectively connected to receive vector data from a vector register, for processing said received vector data and for sending the result of processing to a vector register; and (3) at least one data transfer circuit for transferring data between said main storage means and said vector registers; first holding means for holding the number of all the vector elements to be processed; second holding means provided for each vector processing unit for holding the number of vector elements to be processed in each processing unit; and means for determining the numbers to be set in the second holding means on the basis of the number set in the first holding means.
Claim 2
Dependent Claim
163 words
A vector processing system comprising: main storage means for storing vector instructions and vector data; a plurality of vector processing units connected to said main storage means for processing different vector elements, each of the vector processing units including: (1) a plurality of vector registers; (2) at least one vector arithmetic unit, selectively connected to receive vector data from a vector register, for processing said received vector data and for sending the result of processing to a vector register; and (3) at least one data transfer circuit for transferring data between said main storage means and said vector registers; first holding means for holding the number of all the vector elements to be processed; second holding means provided for each vector processing unit for holding the number of vector elements to be processed in each processing unit; and means for determining the numbers to be set in the second holding means on the basis of the number set in the first holding means.
Claim 3
Dependent Claim
49 words
A vector processing apparatus according to claim 1, wherein said second holding means comprises means for counting down by one each time one vector element is processed in the corresponding vector processing unit and means for detecting when the content of the second holding means reaches a predetermined value.
Claim 4
Dependent Claim
40 words
A vector processing apparatus according to claim 1, wherein each vector processing unit includes a plurality of vector arithmetic units and a second holding means is provided for each of said vector arithmetic units in the corresponding vector processing unit.
Claim 5
Dependent Claim
40 words
A vector processing apparatus according to claim 1, wherein each vector processing unit includes a plurality of data transfer circuits and a second holding means is provided for each of said data transfer circuits in the corresponding vector processing unit.
Claim 6
Dependent Claim
143 words
A vector processing system comprising: a main storage; a plurality of vector processing units connected to said main storage for performing processing on respectively different vector elements, each of said vector processing units including: (1) a plurality of vector registers; (2) at least one vector arithmetic unit, selectively connected to receive vector data from a vector register, for processing said received vector data and for sending the result of processing to a vector register; and (3) at least one data transfer circuit for transferring data between said main storage means and said vector registers; control means for controlling said plurality of vector processing units to execute vector instructions read from said main storage, including means for supplying to the vector processing units addresses of the main storage for mutually different vector elements so that the vector processing units process mutually different vector elements.
Claim 7
Dependent Claim
143 words
A vector processing system comprising: a main storage; a plurality of vector processing units connected to said main storage for performing processing on respectively different vector elements, each of said vector processing units including: (1) a plurality of vector registers; (2) at least one vector arithmetic unit, selectively connected to receive vector data from a vector register, for processing said received vector data and for sending the result of processing to a vector register; and (3) at least one data transfer circuit for transferring data between said main storage means and said vector registers; control means for controlling said plurality of vector processing units to execute vector instructions read from said main storage, including means for supplying to the vector processing units addresses of the main storage for mutually different vector elements so that the vector processing units process mutually different vector elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |