Patent US4684970A successfully refreshed from Google Patents.
US4684970A
Expired / Lapsed
US
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High current lateral transistor structure
Assignee: Intersil Corp
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Filing: 1986-07-21
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Granted: 1987-08-04
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Expires: 2006-07-21
Abstract
Abstract A high current lateral transistor for an integrated circuit device is disclosed. The emitter and collector regions extend into the base region for a distance of approximately one half the thickness of the base region. A second region of the same conductivity type as the collector, surrounds the collector and is spaced therefrom. The base contact shorts together this second region and the base region so that when the transistor goes into saturation excess current will not flow into the substrate.
Inventors
- 👤 Maurice W. Sloane
- 👤 Thomas V. Sikina
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:40
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
266 words
A high current lateral bipolar transistor for use in an integrated circuit comprising: (a) a substrate of a first conductivity type semiconducting material; (b) a first layer of a second conductivity type semiconducting material disposed on said substrate having a surface and a thickness extending from said surface to said substrate; (c) a first region, being an emitter of said transistor, of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer and extending downwardly from said surface for a distance equal to a portion of said thickness; (d) a second region, being a collector of said transistor, of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer spaced from and surrounding said first region and extending downwardly from said surface for a distance equal to said portion of said thickness; (e) a third region of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer spaced from and surrounding said second region and extending downwardly from said surface; (f) a second layer of highly doped second conductivity type semiconducting material intermediate a portion of said substrate and said first layer and being spaced from and opposed to said first, second, and third regions; (g) a fourth region of highly doped second conductivity type disposed within said first layer extending downwardly from said surface; and (h) conductor means for electrically connecting said third and four regions, wherein said third region is adapted to conduct excess current between said first region and said fourth region.
Claim 2
Dependent Claim
266 words
A high current lateral bipolar transistor for use in an integrated circuit comprising: (a) a substrate of a first conductivity type semiconducting material; (b) a first layer of a second conductivity type semiconducting material disposed on said substrate having a surface and a thickness extending from said surface to said substrate; (c) a first region, being an emitter of said transistor, of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer and extending downwardly from said surface for a distance equal to a portion of said thickness; (d) a second region, being a collector of said transistor, of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer spaced from and surrounding said first region and extending downwardly from said surface for a distance equal to said portion of said thickness; (e) a third region of highly doped first conductivity type disposed within and in PN junction forming relation with said first layer spaced from and surrounding said second region and extending downwardly from said surface; (f) a second layer of highly doped second conductivity type semiconducting material intermediate a portion of said substrate and said first layer and being spaced from and opposed to said first, second, and third regions; (g) a fourth region of highly doped second conductivity type disposed within said first layer extending downwardly from said surface; and (h) conductor means for electrically connecting said third and four regions, wherein said third region is adapted to conduct excess current between said first region and said fourth region.
Claim 3
Dependent Claim
49 words
The transistor set forth in claim 1 wherein said first, second, and third regions and said first layer have relative doping levels so that when said transistor is in saturation, current will flow between said first and third regions thereby negating current flow between said transistor and said substrate.
Claim 4
Dependent Claim
24 words
The transistor set forth in claim 2 wherein said portion of said thickness is about one half of said thickness of said first layer.
Claim 5
Dependent Claim
27 words
The transistor set forth in claim 3 wherein said third region extends downwardly from said surface for a distance about equal to said portion of said thickness.
Claim 6
Dependent Claim
39 words
The transistor set forth in claim 4 wherein said third region extends downwardly from said surface for a distance greater than the distance to which the first and second regions extend and surrounds said first, second, and fourth regions.
Claim 7
Dependent Claim
23 words
The transistor set forth in claim 4 wherein said fourth region extends downwardly from said surface into electrical communication with said second layer.
Claim 8
Dependent Claim
32 words
The transistor set forth in claim 6 wherein said first, second, and third regions are of P type conductivity having an electrical resistance of from about 2 to 200 ohms per square.
Claim 9
Dependent Claim
39 words
The transistor set forth in claim 7 including a fifth region of highly doped P type conductivity extending downwardly from said surface into electrical communication with said substrate, said fifth region surrounding said first, second, third, and fourth regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |