CCD output signal processing circuit for use in an image pick-up device

Claim 2

A CCD output signal generating circuit comprising: a CCD type charge transfer device for transferring and outputting signal charges in response to a drive signal of a frequency f c ; an output circuit for generating an output signal corresponding to output signal charges from said CCD type charge transfer device; a low-pass filter circuit, having a cut-off frequency limited to a range of 2f c to 6f c , which is connected to said output circuit and eliminates a high frequency component over the cut-off frequency of an output signal from said output circuit; and a correlated double sampling circuit, connected to said low-pass filter circuit, for sampling and holding an output signal from said low-pass filter circuit.

Claim 3

A circuit according to claim 1, wherein the cut-off frequency of said low-pass filter circuit is set specifically within a range of 2.5f c to 4f c .

Claim 4

A circuit according to claim 2, wherein said CCD type charge transfer device includes a floating diffusion region, connected to supply signal charges to said output circuit, a CCD register for transferring signal charges into said floating diffusion region in response to said drive signal, a drain region set at a reset potential, and a reset gate for selectively coupling said floating diffusion region to said drain region in response to a reset pulse; wherein each operation cycle is divided into a reset period in which said reset pulse is applied to said reset gate, a feed-through level set period in which said reset pulse is interrupted to separate said floating diffusion region from said drain region and a signal level set period in which signal charges are transferred from said CCD register into said floating diffusion region in response to said drive signal; and wherein said charge transfer device generates the output signal charges corresponding to a reset potential, a feed-through potential and a signal potential in said respective periods, said output circuit comprising a switching MOS transistor connected in series between first and second power source terminals and which receives, at its gate, the output signal charges from said charge transfer device and resistive means, and wherein an output voltage is supplied to said low-pass filter circuit from a junction between said switching MOS transistor and said resistive means.

Claim 5

A circuit according to claim 3, wherein said correlated double sampling circuit comprises a clamping circuit connected to said low-pass filter circuit for clamping the output signal generated from said low-pass filter circuit at a predetermined voltage level for said feed-through level set period in addition to generating an output voltage corresponding to the output signal generated from the low-pass filter circuit for said signal level set period, and a sample-hold circuit for sampling and holding the output voltage from said clamping circuit for said signal level set period.

Claim 6

A circuit according to claim 4, wherein said clamping circuit has a capacitor whose one end is connected to said low-pass filter circuit and has first switching means connected between the other end of said capacitor and a reference potential terminal, and wherein said sample-hold circuit has second switching means whose one end is connected to the other end of said capacitor and has a capacitor connected between the other end of said second switching means and said reference potential terminal.

Claim 7

A circuit according to claim 1, wherein said CCD type charge transfer device includes a floating diffusion region, connected to supply signal charges to said output circuit, a CCD register for transferring signal charges into said floating diffusion region in response to said drive signal, a drain region set at a reset potential, and a reset gate for selectively coupling said floating diffusion region to said drain region in response to a reset pulse; wherein each operation cycle is divided into a reset period in which said reset pulse is applied to said reset gate, a feed-through level set period in which said reset pulse is interrupted to separate said floating diffusion region from said drain region and a signal level set period in which signal charges are transferred from said CCD register into said floating diffusion region in response to said drive signal; and wherein said charge transfer device generates the output signal charges corresponding to a reset potential, a feed-through potential and a signal potential in said respective periods, said output circuit comprising a switching MOS transistor connected in series between first and second power source terminals and which receives, at its gate, the output signal charges from said charge transfer device and resistive means, and wherein an output voltage is supplied to said low-pass filter circuit from a junction between said switching MOS transistor and said resistive means.

Claim 8

A circuit according to claim 6, wherein said correlated double sampling circuit comprises a clamping circuit connected to said low-pass filter circuit for clamping the output signal generated from said low-pass filter circuit at a predetermined voltage level for said feed-through level set period in addition to generating an output voltage corresponding to the output signal generated from the low-pass filter circuit for said signal level set period, and a sample-hold circuit for sampling and holding the output voltage from said clamping circuit for said signal level set period.

Claim 9

A circuit according to claim 7, wherein said clamping circuit has a capacitor whose one end is connected to said low-pass filter circuit and has first switch means connected between the other end of said capacitor and a reference potential terminal, and said sample-hold circuit has second switching means whose one end is connected to the other end of said capacitor and has a capacitor connected between the other end of said second switching means and said reference potential terminal.

Claim 10

A circuit according to claim 3 wherein said resistive means is a load MOS transistor having one end connected to said first power source terminal through said switching MOS transistor and having the other end grounded and connected to the gate of said load MOS transistor.

Claim 11

A circuit according to claim 6 wherein said resistive means is a load MOS transistor having one end connected to said first power source terminal through said switching MOS transistor and having the other end grounded and connected to the gate of said load MOS transistor.