US4683437A
Expired / Lapsed
US
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Frequency subtractor
Assignee: Motorola Solutions Inc
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Filing: 1986-06-06
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Granted: 1987-07-28
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Expires: 2006-06-06
Abstract
Abstract A method and apparatus are disclosed for electronically processing a variable frequency input signal and a reference input signal to develop an output signal representative of the frequency difference between the two input signals. The state of the variable frequency signal is sampled upon the occurrence of each leading edge of the reference signal to produce a first output signal. The state of the variable frequency signal is also sampled upon the occurrence of each trailing edge of the reference signal to produce a second output signal. The two output signals are preferably ORed to develop the final output signal.
Inventors
- 👤 Rupin J. Javeri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:05
CPC Classifications
H; H03; H03B; H03B21/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
118 words
A method of processing a sense signal and a reference signal that has leading and trailing edges to develop an output signal representative of the difference in frequency between the reference signal and the sense signal, comprising: sampling the sense signal upon the occurrence of each leading edge of the reference signal so as to develop a first binary signal whose state depends on the sampled state of the sense signal; sampling the sense signal upon the occurrence of each trailing edge of the reference signal so as to develop a second binary signal whose state depends on the sampled state of the sense signal; and logically ORing the first and second signals to develop the output signal.
Claim 2
Independent Claim
118 words
A method of processing a sense signal and a reference signal that has leading and trailing edges to develop an output signal representative of the difference in frequency between the reference signal and the sense signal, comprising: sampling the sense signal upon the occurrence of each leading edge of the reference signal so as to develop a first binary signal whose state depends on the sampled state of the sense signal; sampling the sense signal upon the occurrence of each trailing edge of the reference signal so as to develop a second binary signal whose state depends on the sampled state of the sense signal; and logically ORing the first and second signals to develop the output signal.
Claim 3
Dependent Claim
47 words
A method as set forth in claim 1 wherein the state of the first binary signal is the same as the sampled state of the sense signal, and wherein the state of the second binary signal is the opposite of the sampled state of the sense signal.
Claim 4
Dependent Claim
53 words
A method as set forth in claim 2 wherein the sense signal corresponds to the output of a sense oscillator, wherein the reference signal corresponds to the output of a reference oscillator, and wherein the frequency of said output signal corresponds to the frequency difference between the sense oscillator and the reference oscillator.
Claim 5
Dependent Claim
118 words
A subtractor for developing an output signal that is representative of the frequency difference between a sense signal and a reference signal that has leading and trailing edges, comprising: first means for sampling the sense signal upon the occurrence of each leading edge of the reference signal so as to develop a first binary signal whose state depends on the sampled state of the sense signal; second means for sampling the sense signal upon the occurrence of each trailing edge of the reference signal so as to develop a second binary signal whose state depends on the sampled state of the sense signal; and means for logically ORing the first and second signals to develop the output signal
Claim 6
Dependent Claim
118 words
A subtractor for developing an output signal that is representative of the frequency difference between a sense signal and a reference signal that has leading and trailing edges, comprising: first means for sampling the sense signal upon the occurrence of each leading edge of the reference signal so as to develop a first binary signal whose state depends on the sampled state of the sense signal; second means for sampling the sense signal upon the occurrence of each trailing edge of the reference signal so as to develop a second binary signal whose state depends on the sampled state of the sense signal; and means for logically ORing the first and second signals to develop the output signal
Claim 7
Dependent Claim
38 words
A subtractor as set forth in claim 4 wherein said first sampling means includes a first flip-flop for sampling the sense signal and wherein said second sampling means includes a second flip-flop for sampling the same sense signal.
Claim 8
Dependent Claim
43 words
A subtractor as set forth in claim 5 wherein said first flip-flop is clocked by the reference signal, wherein the second sampling means includes an inverter for inverting the reference signal, and wherein the second flip-flop is clocked by the inverted reference signal.
Claim 9
Dependent Claim
41 words
A subtractor as set forth in claim 6 wherein the first flip-flop has a Q output, wherein the second flip-flop has a not Q output, and wherein said Q and not Q outputs correspond to said first and second binary signals.
Claim 10
Dependent Claim
128 words
A subtractor for developing an output signal that is representative of the frequency difference between a sense signal and reference signal, comprising: a first flip-flop receiving the sense signal and being clocked in synchronism with the reference signal for developing a first signal that is representative of the frequency difference between the sense signal and the reference signal and that has amplitude transitions between high and low levels; a second flip-flop receiving the sense signal and being clocked in sychronism with the reference signal for developing a second signal having amplitude transitions that are offset from the amplitude transitions of the first signal by one-half the period of the reference signal; and means for combining the first and second signals to develop an output signal with reduced jitter.
Claim 11
Dependent Claim
128 words
A subtractor for developing an output signal that is representative of the frequency difference between a sense signal and reference signal, comprising: a first flip-flop receiving the sense signal and being clocked in synchronism with the reference signal for developing a first signal that is representative of the frequency difference between the sense signal and the reference signal and that has amplitude transitions between high and low levels; a second flip-flop receiving the sense signal and being clocked in sychronism with the reference signal for developing a second signal having amplitude transitions that are offset from the amplitude transitions of the first signal by one-half the period of the reference signal; and means for combining the first and second signals to develop an output signal with reduced jitter.
Claim 12
Dependent Claim
16 words
A subtractor as set forth in claim 8 wherein said combining means comprises an OR gate.
Claim 13
Dependent Claim
23 words
A subtractor as set forth in claim 8 wherein said first and second flip-flops are clocked on different transitions of the reference signal.
Claim 14
Dependent Claim
119 words
A subtractor for developing an output signal that is representative of the frequency difference between a first signal and a second signal that has leading and trailing edges, comprising: first means for sampling the first signal upon the occurence of each leading edge of the second signal so as to develop a first binary signal whose state depends on the sampled state of the first signal; second means for sampling the first signal upon the occurence of each trailing edge of the second signal so as to develop a second binary signal whose state depends on the sampled state of the first signal; and means for logically ORing the first and second binary signals to develop the output signal.
Claim 15
Dependent Claim
119 words
A subtractor for developing an output signal that is representative of the frequency difference between a first signal and a second signal that has leading and trailing edges, comprising: first means for sampling the first signal upon the occurence of each leading edge of the second signal so as to develop a first binary signal whose state depends on the sampled state of the first signal; second means for sampling the first signal upon the occurence of each trailing edge of the second signal so as to develop a second binary signal whose state depends on the sampled state of the first signal; and means for logically ORing the first and second binary signals to develop the output signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-27 | 1991-01-26 | 1991-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-27 | 1995-01-26 | 1995-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-27 | 1999-01-26 | 1999-07-28 | $7700.00 | Window Closed / Lapsed |