US4050024A
Expired / Lapsed
US
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Sideband detector
Assignee: Tektronix Inc
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Filing: 1975-10-02
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Granted: 1977-09-20
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Expires: 1995-10-02
Abstract
Abstract A sideband detector capable of detecting one of two mixing products and disregarding the other is provided. The characteristic of the invention is provided by feeding a sequential logic mixer in each of two channels by the output of a reference source which feeds one channel in phase and delayed to the second. An input signal is also simultaneously applied to both of the mixers. The mixer outputs then feed a sequential logic circuit for detecting the desired sideband.
Inventors
- 👤 Fendall Gregory Winston, IV
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:14
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; G; G01; G01R; G01R23/00; G01R23/16; G01R23/175; H03D; H03D7/00; H03D7/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
A sideband detector, comprising: delay means responsive to a first signal for delaying said first signal; first mixer means including first digital sequential logic flip-flop means responsive to the delayed signal and to a second signal for providing a first mixed signal; second mixer means including second digital sequential logic flip-flop means responsive to both said first and said second signals for providing a second mixed signal; and digital detector means defining a sequential logic flip-flop responsive to both said first and said second mixed signals for detecting one sideband of the mixed signals.
Claim 2
Dependent Claim
94 words
A sideband detector, comprising: delay means responsive to a first signal for delaying said first signal; first mixer means including first digital sequential logic flip-flop means responsive to the delayed signal and to a second signal for providing a first mixed signal; second mixer means including second digital sequential logic flip-flop means responsive to both said first and said second signals for providing a second mixed signal; and digital detector means defining a sequential logic flip-flop responsive to both said first and said second mixed signals for detecting one sideband of the mixed signals.
Claim 3
Independent Claim
92 words
The method of sideband detecting, comprising: applying a first signal to a digital delay means for providing a delayed signal; applying said delayed signal and a second signal to a first digital sequential logic flip-flop mixer means for providing a first mixed signal; applying both said first and said second signals to a second digital sequential logic flip-flop mixer means for providing a second mixed signal; and applying both said first and said second mixed signals to a digital sequential logic flip-flop detector means for detecting one sideband of the mixed signals.
Claim 4
Independent Claim
92 words
The method of sideband detecting, comprising: applying a first signal to a digital delay means for providing a delayed signal; applying said delayed signal and a second signal to a first digital sequential logic flip-flop mixer means for providing a first mixed signal; applying both said first and said second signals to a second digital sequential logic flip-flop mixer means for providing a second mixed signal; and applying both said first and said second mixed signals to a digital sequential logic flip-flop detector means for detecting one sideband of the mixed signals.
Claim 5
Dependent Claim
105 words
A frequency locking system, comprising: reference signal generating means for generating a reference signal; controlled signal generating means for generating a variable signal, said controlled signal generating means including means for varying said variable signal; means including digital sequential logic flip-flop means responsive to both said reference signal and said variable signal for providing a control signal; and feedback means disposed between said controlled signal generating means and said means including digital sequential logic flip-flop means for applying said control signal to said means for varying to cause said variable signal to be varied until said variable signal is frequency locked to said reference signal.
Claim 6
Dependent Claim
105 words
A frequency locking system, comprising: reference signal generating means for generating a reference signal; controlled signal generating means for generating a variable signal, said controlled signal generating means including means for varying said variable signal; means including digital sequential logic flip-flop means responsive to both said reference signal and said variable signal for providing a control signal; and feedback means disposed between said controlled signal generating means and said means including digital sequential logic flip-flop means for applying said control signal to said means for varying to cause said variable signal to be varied until said variable signal is frequency locked to said reference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-19 | 1981-03-21 | 1981-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-19 | 1985-03-21 | 1985-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-19 | 1989-03-21 | 1989-09-20 | $7700.00 | Window Closed / Lapsed |