Processing circuit with asymmetry corrector and convolutional encoder for digital data

Claim 1

A circuit for correcting input parameter variations in incoming signals of simultaneously transmitted but separately propagated data and clock pulse bits and for convolutionaly encoding the corrected signal, comprising: (a) corrector means for providing a series of corrected data pulses at the incoming data rate to an encoder, wherein the corrector means comprises; (1) means for receiving the incoming clock pulse bits; (2) means for forming from the received clock pulse bits a regenerated clock signal, said forming means having frequency adjustment means whereby, frequency of regenerated clock signal is adjusted to coincide with the received clock signal; (3) means for receiving the data pulse bits; (4) phase adjusting means for adjusting the phase of the regenerated clock signal relative to the received data signal to maintain phase coincidence; (5) mislock detector means for detecting and correcting a possible mislock condition whenever the phase adjustment means and the frequency adjustment means cooperate to create a false frequency lock between the received clock pulses and the regenerated clock signal, (b) a convolutional encoder for encoding a series of digital data pulses, comprising: (1) means for receiving the series of data pulses; (2) means for encoding the series of data pulses to produce an encoded data stream wherein each bit of the series of data pulses is represented by two bits of the encoded data stream, and wherein the means for encoding further comprises; (3) main register means for receiving and storing a series of a plurality of data pulses in corresponding number of shift register stages; (4) first means for modulo-two adding the contents of a first group of selected ones of the shift register stages; (5) second means for modulo-two adding the contents of a second group of selected ones of the shift register stages, said first and second groups being equal in number and differing from each other by at least one shift register stage; (6) storage means for separately and serially loading the outputs of said first and second means for modulo-two adding; (7) parallel register means for parallel loading the contents of said storage means; (8) said parallel register means further comprising means for serially transferring out the signals stored therein as coded digital data pulses.