Patent US3349402A successfully refreshed from Google Patents.
US4682292A
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Fault tolerant flight data recorder
Assignee: RTX Corp
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Filing: 1984-07-23
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Granted: 1987-07-21
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Expires: 2004-07-23
Abstract
Abstract Signal units of information stored in electronic memory are arranged in frames which are separated in memory by configurable end of data pointers, each frame stored with a first configuration pointer indicating a present frame, the storing of each present frame changing the preceding frame pointer to a second configuration, whereby loss of frame data due to power interruption during storage is limited to the identifiable present frame.
Inventors
- 👤 Richard L. Bue
- 👤 Ratchford Michael
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:57
CPC Classifications
G; G07; G07C; G07C5/00; G07C5/08; G07C5/0841; G07C5/085
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
The method of storing serial bit data signal units in electronic memory, comprising the steps of: arranging the data signal units in successive frames, serially, from a data signal unit to a last data signal unit in each frame; adding first and second pointer signal units following said last data signal unit in each frame, said first pointer and second pointer signal units and said data signal units each having a plurality of signal bits; and storing the frames at successive memory address locations in electronic memory, by first storing said second pointer signal unit of a present frame to a first address location furthest from a preceding stored frame, and proceeding serially backwards with the data signal units until said first data signal unit of the present frame is stored at the address location of said second pointer signal unit of said preceding stored frame to replace said second pointer signal unit of said preceding stored frame, whereby said present frame is stored with said first and second pointer signal units and said preceding stored frames are stored with said first pointer signal unit.
Claim 2
Independent Claim
185 words
The method of storing serial bit data signal units in electronic memory, comprising the steps of: arranging the data signal units in successive frames, serially, from a data signal unit to a last data signal unit in each frame; adding first and second pointer signal units following said last data signal unit in each frame, said first pointer and second pointer signal units and said data signal units each having a plurality of signal bits; and storing the frames at successive memory address locations in electronic memory, by first storing said second pointer signal unit of a present frame to a first address location furthest from a preceding stored frame, and proceeding serially backwards with the data signal units until said first data signal unit of the present frame is stored at the address location of said second pointer signal unit of said preceding stored frame to replace said second pointer signal unit of said preceding stored frame, whereby said present frame is stored with said first and second pointer signal units and said preceding stored frames are stored with said first pointer signal unit.
Claim 3
Dependent Claim
45 words
The method of claim 1, wherein said step of adding further comprises the step of: setting the signal bits of said first and second pointer signal units to a common logic state which is different from that allowed to occur for said data signal units.
Claim 4
Dependent Claim
120 words
The method of claim 1, wherein the step of storing comprises the steps of: buffering each stored frame in a signal buffer; comparing each data signal unit of each stored frame in memory with the corresponding data signal unit in said signal buffer; identifying each address location of each data signal unit having a data content different from that of its corresponding signal unit in said buffer, as a failed address location; extending said first address location to a next succeeding location which is further from said first address location by a number of address locations equal to the number of said failed address locations; rewriting said stored frame to memory in sequence after skipping over said failed address locations.
Claim 5
Dependent Claim
122 words
The method of claim 1, further comprising, prior to said step of storing, the steps of: mapping the storage location of each present frame in memory to determine a number of successive mapped address locations, beginning with the address location of said second pointer signal unit of said preceding frame, and ending at an address location coincident with said second pointer signal unit of said present frame; comparing said mapped locations with a tabulation of known failed address locations, to detect any coincidence therebetween; and extending said first address location to a next succeeding address location distant therefrom by the number of said detected failed address locations, wherein said present frame is stored in sequence after skipping over said failed address locations.
Claim 6
Dependent Claim
54 words
The method of claim 1, further comprising, prior to said step of storing, the step of: adding as said last signal unit in each present frame to be stored in memory, an error checking code signal unit for use in determining the data accuracy of each stored frame following retrieval thereof from the memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-20 | 1991-01-19 | 1991-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-20 | 1995-01-19 | 1995-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-20 | 1999-01-19 | 1999-07-21 | $7700.00 | Window Closed / Lapsed |