Patent US4680793A successfully refreshed from Google Patents.
US4680793A
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US
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Noise eliminating circuit
Assignee: Pioneer Corp
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Filing: 1985-04-24
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Granted: 1987-07-14
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Expires: 2005-04-24
Abstract
Abstract A noise eliminating circuit including a subsignal modulator circuit, a matrix circuit, and sample-and-hold circuits, for reducing signal distortion as well as preventing the in-circuit generation of noise. The sample-and-hold circuits are disposed in the signal paths of a main signal and the demodulated subsignal and are operated by a signal synchronous with a noise component. The holding times of the two sample-and-hold circuits may be made different from one another.
Inventors
- 👤 Yoshiro Sugai
- 👤 Hiroyuki Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:38
CPC Classifications
H; H04; H04H; H04H40/00; H04H40/18; H04H40/27; H04H40/36; H04H40/45; H04H40/54; H03; H03D; H03D1/00; H03D1/22; H03D1/2209; H03D1/2236; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/1661; H04B1/1669; H04B1/1676; H04H40/72; H04N; H04N5/00; H04N5/44; H04N5/60; H04N5/607
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
A noise eliminating circuit for use in a TV audio multi-demodulator circuit, said noise eliminating circuit comprising: a subsignal demodulator circuit for demodulating a subsignal from a composite multiplexed signal containing a main signal and a subsignal, a matrix circuit for effecting arithmetic operations upon said main signal and the demodulated subsignal from said subsignal demodulator circuit to produce first and second output signals, and sample-and-hold circuit means interposed between said subsignal demodulator circuit and said matrix circuit in a signal path of said subsignal for sampling and holding said demodulated subsignal in response to a signal synchronized with at least one of a noise detection signal and a noise component contained in said subsignal, noise elimination being performed only on said demodulated subsignal in said TV audio multi-demodulator circuit, said main signal being passed to said matrix circuit without having noise elimination performed thereon.
Claim 2
Dependent Claim
145 words
A noise eliminating circuit for use in a TV audio multi-demodulator circuit, said noise eliminating circuit comprising: a subsignal demodulator circuit for demodulating a subsignal from a composite multiplexed signal containing a main signal and a subsignal, a matrix circuit for effecting arithmetic operations upon said main signal and the demodulated subsignal from said subsignal demodulator circuit to produce first and second output signals, and sample-and-hold circuit means interposed between said subsignal demodulator circuit and said matrix circuit in a signal path of said subsignal for sampling and holding said demodulated subsignal in response to a signal synchronized with at least one of a noise detection signal and a noise component contained in said subsignal, noise elimination being performed only on said demodulated subsignal in said TV audio multi-demodulator circuit, said main signal being passed to said matrix circuit without having noise elimination performed thereon.
Claim 3
Dependent Claim
28 words
The noise eliminating circuit as claimed in claim 1, further comprising first and second de-emphasis circuits disposed in signal paths of said main signal and said subsignal, respectively.
Claim 4
Dependent Claim
149 words
A noise eliminating circuit comprising: a subsignal demodulator circuit for demodulating a subsignal from a composite multiplexed signal containing a main signal and a subsignal, a matrix circuit for effecting arithmetic operations upon said main signal and the demodulated subsignal from said subsignal demodulation circuit to produce first and second output signals, and first and second sample-and-hold circuit means interposed, respectively, in a signal path of said main signal prior to said matrix circuit and in a signal path of said subsignal between said subsignal demodulator circuit and said matrix circuit for sampling and holding said main signal and said subsignal in response to a signal synchronized with at least one of a noise detection signal and a noise component contained in one of said main signal and said subsignal, a hold time of said second sample-and-hold circuit being longer than a hold time of said first sample-and-hold circuit.
Claim 5
Dependent Claim
149 words
A noise eliminating circuit comprising: a subsignal demodulator circuit for demodulating a subsignal from a composite multiplexed signal containing a main signal and a subsignal, a matrix circuit for effecting arithmetic operations upon said main signal and the demodulated subsignal from said subsignal demodulation circuit to produce first and second output signals, and first and second sample-and-hold circuit means interposed, respectively, in a signal path of said main signal prior to said matrix circuit and in a signal path of said subsignal between said subsignal demodulator circuit and said matrix circuit for sampling and holding said main signal and said subsignal in response to a signal synchronized with at least one of a noise detection signal and a noise component contained in one of said main signal and said subsignal, a hold time of said second sample-and-hold circuit being longer than a hold time of said first sample-and-hold circuit.
Claim 6
Dependent Claim
28 words
The noise eliminating circuit as claimed in claim 3, further comprising first and second de-emphasis circuits disposed in signal paths of said main signal and said subsignal, respectively.
Claim 7
Dependent Claim
36 words
The noise eliminating circuit as claimed in claim 3, further comprising first and second low-pass filters disposed in signal paths of said main signal and said subsignal, respectively, prior to said first and second sample-and-hold circuits.
Claim 8
Dependent Claim
25 words
The noise eliminating circuit as claimed in claim 5, wherein said first and second sample-and-hold circuits comprise capacitive holding elements with substantially no series resistance.
References Cited (Backward Citations)
US4314377A
Cited
US4574390A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |