US4680723A
Expired / Lapsed
US
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Signal processor for matrix arrays
Assignee: MBDA UK Ltd
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Filing: 1984-10-11
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Granted: 1987-07-14
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Expires: 2004-10-11
Abstract
Abstract Matrix arrays, in particular infra-red arrays, suffer from non-uniformity in output from the individual elements in the array. This is due to each element in the array having for example, its own characteristic responsivity and leakage current, and is seen in the array output as a pattern of offset values. These offset values must be removed from the output of the array if useful digital information is to be obtained. One known method of doing this is to show the array a black body at a known uniform temperature and use the output from the array to cancel the offset values. However, the dynamic range of the system is directly related to the range of offset values obtained and also to the size of the digitizer. Large-size digitizers have relatively slow sampling rates and in order to have a higher sampling rate, a small-size digitizer must be used. The signal processing system described herein corrects for offset values and is able to provide a high sampling rate by using a small-size digitizer.
Inventors
- 👤 David T. Whinray
- 👤 Gwilym J. Tilsley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:11
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/63; H04N5/00; H04N5/30; H04N5/33
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
281 words
A signal processing system for applying offsets to analog input signals received one after another from a plurality of signal forming elements to compensate for any differences in the characteristics of the different elements, the system comprising: subtracting means having a first input for receiving said analog input signals and having a second input for receiving further analog signals for forming difference signals dependent upon said input signals minus values dependent upon said further analog signals; N-bit analog to digital converter means connected to the subtracting means for forming N-bit digital signals representative of successive samples of said difference signals; digital signal adding means having two inputs and an output, one of said two inputs being connected to the analog to digital converter means for receiving said N-bit digital signals and the adding means supplying at its output the sum values of signals applied to its two inputs; store means connected to the output and the other of said two inputs of the adding means, the store means having a plurality of storage locations corresponding to respective ones of said signal forming elements for storing at said locations respective sum values received from the output of the adding means and also for supplying the stored sum values to said other input of the adding means to initiate the formation of new sum values by the adding means; and M-bit digital to analog converter means connected to said store means and said second input of the substracting means for receiving M-bit digital sum values read from the storage locations of the store means and for converting them to form said further analog signals, the number of bits M being greater than N.
Claim 2
Dependent Claim
281 words
A signal processing system for applying offsets to analog input signals received one after another from a plurality of signal forming elements to compensate for any differences in the characteristics of the different elements, the system comprising: subtracting means having a first input for receiving said analog input signals and having a second input for receiving further analog signals for forming difference signals dependent upon said input signals minus values dependent upon said further analog signals; N-bit analog to digital converter means connected to the subtracting means for forming N-bit digital signals representative of successive samples of said difference signals; digital signal adding means having two inputs and an output, one of said two inputs being connected to the analog to digital converter means for receiving said N-bit digital signals and the adding means supplying at its output the sum values of signals applied to its two inputs; store means connected to the output and the other of said two inputs of the adding means, the store means having a plurality of storage locations corresponding to respective ones of said signal forming elements for storing at said locations respective sum values received from the output of the adding means and also for supplying the stored sum values to said other input of the adding means to initiate the formation of new sum values by the adding means; and M-bit digital to analog converter means connected to said store means and said second input of the substracting means for receiving M-bit digital sum values read from the storage locations of the store means and for converting them to form said further analog signals, the number of bits M being greater than N.
Claim 3
Dependent Claim
34 words
A system according to claim 1, wherein dividing means are included between the analog-to-digital converting means and the adding means to provide an integration time constant which determines the decay rate of the system.
Claim 4
Dependent Claim
14 words
A system according to claim 2, wherein the dividing means has a fixed value.
Claim 5
Dependent Claim
14 words
A system according to claim 2, wherein the dividing means has a variable value.
Claim 6
Dependent Claim
20 words
A system according to claim 1, wherein N has the value of 8 and M has the value of 12.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |