US4678935A
Expired / Lapsed
US
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Inner bias circuit for generating ECL bias voltages from a single common bias voltage reference
Assignee: Fujitsu Ltd
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Filing: 1984-09-14
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Granted: 1987-07-07
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Expires: 2004-09-14
Abstract
Abstract An integrated circuit device having a simplified bias supply circuit for supplying bias power sources for a plurality of circuit units or cell units. The integrated circuit device cmprises: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line; and one or more common bias generating portions disposed at the periphery of the cell unit array, each of the common bias generating portions generating a single common bias voltage which differs from the potential of the second power supply line by a constant value. Each of the cell units comprises one or more logic circuit cells such as ECL type logic circuits, and an inner bias circuit which receives the common bias voltage and which generates a first inner bias voltage and a second inner bias voltage that are supplied to the respective logic circuit cell. The second inner bias voltage differs from the common bias voltage by a constant value, and the first inner bias voltage differs from the potential of the first power supply line at the cell unit by the value determined by the values of the elements in the inner bias circuit and by the common bias voltage.
Inventors
- 👤 Kazumasa Nawata
- 👤 Yasunori Kanai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:03
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
267 words
An integrated circuit device comprising: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line on said chip; and at least one common bias generating portion disposed on said chip at the periphery of said cell unit array, each said common bias generating portion generating a respective single common bias voltage which differs from the potential of said second power supply line by a first constant value; each of said cell units including: at least one logic circuit portion each having at least a pair of logic transistors which are connected to said first power supply line and whose emitters are mutually connected, and a constant current source means connected to said second power supply line for supplying a constant current to said logic transistors; and an inner bias circuit which receives said common bias voltage and which generates a first inner bias voltage that is supplied to the base of a first one of the logic transistors and a second inner bias voltage that is supplied to said constant current source means; wherein the value of the respective second inner bias voltage differs from said common bias voltage by a second constant value, and the value of the respective first inner bias voltage differs from the potential of said first power supply line at the respective cell unit by a value determined according to the characteristic values of elements in the respective inner bias circuit and by said common bias voltage at the respective cell unit.
Claim 2
Dependent Claim
267 words
An integrated circuit device comprising: a cell unit array having a plurality of cell units disposed in a central portion of a semiconductor chip; a first power supply line and a second power supply line on said chip; and at least one common bias generating portion disposed on said chip at the periphery of said cell unit array, each said common bias generating portion generating a respective single common bias voltage which differs from the potential of said second power supply line by a first constant value; each of said cell units including: at least one logic circuit portion each having at least a pair of logic transistors which are connected to said first power supply line and whose emitters are mutually connected, and a constant current source means connected to said second power supply line for supplying a constant current to said logic transistors; and an inner bias circuit which receives said common bias voltage and which generates a first inner bias voltage that is supplied to the base of a first one of the logic transistors and a second inner bias voltage that is supplied to said constant current source means; wherein the value of the respective second inner bias voltage differs from said common bias voltage by a second constant value, and the value of the respective first inner bias voltage differs from the potential of said first power supply line at the respective cell unit by a value determined according to the characteristic values of elements in the respective inner bias circuit and by said common bias voltage at the respective cell unit.
Claim 3
Dependent Claim
61 words
An integrated circuit device according to claim 1, wherein each said inner bias circuit comprises: a first transistor whose base receives said common bias voltage and whose emitter outputs the respective second inner bias voltage; and a second transistor whose base is connected to the collector of the respective first transistor and whose emitter outputs the respective first inner bias voltage.
Claim 4
Dependent Claim
53 words
An integrated circuit device according to claim 2, wherein each said inner bias circuit further comprises a third transistor whose collector is connected to the emitter of the respective sound transistor, whose base is connected to the base of the respective first transistor and whose emitter outputs the respective second inner bias voltage.
Claim 5
Dependent Claim
44 words
An integrated circuit device according to claim 2, wherein each said inner bias circuit further comprises a third transistor whose collector is connected to the emitter of the respective second transistor and whose base is connected to the emitter of the respective first transistor.
Claim 6
Dependent Claim
38 words
An integrated circuit device according to claim 2 or 3 or 4, wherein each said inner bias circuit further comprises a collector resistor connected between the collector of the respective first transistor and said first power supply line.
Claim 7
Dependent Claim
32 words
An integrated circuit device according to claim 5, wherein each said collector resistor has approximately a first resistance value independently of the location of the respective cell unit on said semiconductor chip.
Claim 8
Dependent Claim
31 words
An integrated circuit device according to claim 5, wherein the resistance of each said collector resistor is adjusted depending on the location of the respective cell unit on said semiconductor chip.
Claim 9
Dependent Claim
62 words
An integrated circuit device according to claim 1, wherein each said logic circuit cell comprises a pair of load resistors having first ends connected to the collectors of respective ones of said logic transistors and whose other ends are mutually connected, and an additional resistor connected between said first power supply line and said mutually connected other ends of said load resistors.
Claim 10
Dependent Claim
31 words
An integrated circuit device according to claim 8, wherein the resistance of each said additional resistor is adjusted depending on the location of the respective cell unit on said semiconductor chip.
Claim 11
Dependent Claim
161 words
An integrated circuit device having a plurality of circuit units each having an input terminal for receiving an input signal and an output terminal for providing an output signal in response to said input signal and a bias supply section for supplying voltage to said plurality of circuit units, said bias supply section comprising a common bias circuit which outputs a predetermined stabilized reference voltage, and a plurality of inner bias circuits, each of which corresponds to at least one of said circuit units, and each of which has at least one resistor and is connected to receive the output of said common bias circuit with a respective line voltage drop and supplies a plurality of predetermined stabilized bias voltages in common to each said corresponding circuit unit according to the value of said predetermined stabilized reference voltage as output by said common bias circuit, said stabilized bias voltages being adjusted so as to compensate for said respective line voltage drops.
Claim 12
Dependent Claim
161 words
An integrated circuit device having a plurality of circuit units each having an input terminal for receiving an input signal and an output terminal for providing an output signal in response to said input signal and a bias supply section for supplying voltage to said plurality of circuit units, said bias supply section comprising a common bias circuit which outputs a predetermined stabilized reference voltage, and a plurality of inner bias circuits, each of which corresponds to at least one of said circuit units, and each of which has at least one resistor and is connected to receive the output of said common bias circuit with a respective line voltage drop and supplies a plurality of predetermined stabilized bias voltages in common to each said corresponding circuit unit according to the value of said predetermined stabilized reference voltage as output by said common bias circuit, said stabilized bias voltages being adjusted so as to compensate for said respective line voltage drops.
Claim 13
Dependent Claim
185 words
An integrated circuit device having a plurality of circuit units each having an input terminal for receiving an input signal and an output terminal for providing an output signal in response to said input signal and a bias supply section for supplying voltage to said plurality of circuit units, said bias supply section comprising a common bias circuit which outputs a predetermined stabilized reference voltage, a plurality of inner bias circuits, each of which corresponds to at least one of said circuit units, and each of which has at least one resistor and is connected to receive the output of said common bias circuit with a respective line voltage drop and supplies a plurality of predetemined stabilized bias voltages in common to each said corresponding circuit unit according to the value of said predetermined stabilized reference voltage as output by said common bias circuit, and at least selected ones of said inner bias circuits have elements of respective values so that the values of the respective stabilized bias voltages supplied from different selected ones of said inner bias circuits are equal, independently of their locations.
Claim 14
Dependent Claim
185 words
An integrated circuit device having a plurality of circuit units each having an input terminal for receiving an input signal and an output terminal for providing an output signal in response to said input signal and a bias supply section for supplying voltage to said plurality of circuit units, said bias supply section comprising a common bias circuit which outputs a predetermined stabilized reference voltage, a plurality of inner bias circuits, each of which corresponds to at least one of said circuit units, and each of which has at least one resistor and is connected to receive the output of said common bias circuit with a respective line voltage drop and supplies a plurality of predetemined stabilized bias voltages in common to each said corresponding circuit unit according to the value of said predetermined stabilized reference voltage as output by said common bias circuit, and at least selected ones of said inner bias circuits have elements of respective values so that the values of the respective stabilized bias voltages supplied from different selected ones of said inner bias circuits are equal, independently of their locations.
Claim 15
Dependent Claim
23 words
The device of claim 11, wherein all of said inner bias circuits output the same values of said plurality of stabilized bias voltages.
Claim 16
Dependent Claim
55 words
The device of claim 11, wherein each said circuit unit has an input terminal for receiving an input digital signal and an output terminal for providing an output digital signal, and said output digital signal of all of said circuit units has the same voltage value for corresponding logic levels of the respective input signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |