Programmable logic controller

Claim 1

A programmable logic controller including: a plurlity of input terminals, a plurality of output terminals, a control memory (10) for storing a sequence of instructions selected from an instruction set consisting of only three different types of instructions, said instruction set including, instructions of a first type (READ) and instructions of a second type (WRITE), each of said first and second types of instructions comprising an operation code, a condition bit and an address field, and instructions of a third type (JUMP), each of said JUMP instructions including an operation code and an address field, and addressing means (IAR) for sequentially addressing said control memory, at a beginning address supplied to said controller, input selecting means (12) for selectively connecting one of said input terminals to a first line (14) in response to the contents of the address field of an instruction read from said control memory, output selecting means (13) for selectively connecting a second line (15) to one of said output terminals in response to the contents of the address field of the instruction read from said control memory, a condition latch (35), settable as a function of the instruction type, the condition bit and the data on said first line, comparing means (29) for comparing the level of said first line with that of said condition bit, decoding means (25) for decoding the operation code of the instruction read from said control memory, means (32) for, in response to the decoding of a first type-instruction by said decoding means, setting the condition latch to a first or a second state depending on whether the result of the comparison provided by the comparing means is affirmative or negative, and means (30, 31, 36, 37) for, in response to the decoding of a second type-instruction by said decoding means, providing the level of said condition bit or its inverse at said second line (15) as a function of whether the condition latch is in a first or second state respectively, and means (38-41) for applying the contents of the address field of said third type-instruction read from said control memory to the addressing means (IAR) if the condition latch is currently set to its first state by a previous instruction.