US4339794A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for controlling input/output in process control
Assignee: Hitachi Ltd
•
Filing: 1979-09-12
•
Granted: 1982-07-13
•
Expires: 1999-09-12
Abstract
Abstract Novel method and system for controlling input/output in a process control wherein state signals of object processes to be controlled are applied to a CPU via a process input/output unit and operated in the CPU in accordance with a logic programmed and stored in advance, and results of the operation are delivered out to the object processes to control the same. A buffer memory is interposed between the CPU and the process input/output unit. While reception and delivery of data are performed between the CPU or processor unit and the buffer memory, fetching of the state signals of the object processes or delivery of the process controlling signals is performed between the buffer memory and the object processes, thereby attaining a high rate processing as viewed from the overall processing of the system.
Inventors
- 👤 Keiji Hideshima
- 👤 Haruo Koyanagi
- 👤 Shuichi Senda
- 👤 Kazuyoshi Asada
- 👤 Norio Murayama
- 👤 Yoshiyuki Nihashi
- 👤 Masaoki Takaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:52
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1159; G05B2219/15; G05B2219/15048
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
235 words
A method for controlling input/output operations in a process wherein signals representative of the states of object processes to be controlled are fetched and are operated upon by a processor unit in accordance with a program stored in advance, and signals representative of the results of the operations are used to control the object processes, said method comprising the steps of: storing sequentially the state signals of the object processes to be controlled in an input region of a buffer memory interposed between the processor unit and a process input/output unit, said buffer memory also having an output region; reading out the state signals of the object processes stored in the buffer memory, causing the processor unit to effect a logical operation processing on the basis of said state signals and storing the results of the logical operation in the output region of the buffer memory, said processor unit accessing the buffer memory randomly; and causing the process input/output unit to read out signals representative of the results of the logical operation stored in the output region of the buffer memory so as to provide signals for controlling the object processes to be controlled, said process input/output unit accessing the buffer memory by scanning thereof in a predetermined sequence; whereby input/output communication of the state signals between the processor unit and the object processes to be controlled is effected by way of the buffer memory.
Claim 2
Independent Claim
235 words
A method for controlling input/output operations in a process wherein signals representative of the states of object processes to be controlled are fetched and are operated upon by a processor unit in accordance with a program stored in advance, and signals representative of the results of the operations are used to control the object processes, said method comprising the steps of: storing sequentially the state signals of the object processes to be controlled in an input region of a buffer memory interposed between the processor unit and a process input/output unit, said buffer memory also having an output region; reading out the state signals of the object processes stored in the buffer memory, causing the processor unit to effect a logical operation processing on the basis of said state signals and storing the results of the logical operation in the output region of the buffer memory, said processor unit accessing the buffer memory randomly; and causing the process input/output unit to read out signals representative of the results of the logical operation stored in the output region of the buffer memory so as to provide signals for controlling the object processes to be controlled, said process input/output unit accessing the buffer memory by scanning thereof in a predetermined sequence; whereby input/output communication of the state signals between the processor unit and the object processes to be controlled is effected by way of the buffer memory.
Claim 3
Dependent Claim
74 words
A method for controlling input/output operations in a process control according to claim 1, wherein the time for the processor unit to access the buffer memory and the time for the process input/output unit to access the buffer memory are predetermined, and accessible time zones are repeated at a period corresponding to the sum of both the times to allow the processor unit and the process input/output unit to access the buffer memory alternately.
Claim 4
Dependent Claim
49 words
A method for controlling input/output operations in a process control according to claim 2, wherein one period of the accessible time is determined on the basis of a timing signal which is generated interiorly of the process input/output unit and is independent of the timing for the processor unit.
Claim 5
Independent Claim
195 words
A system for controlling input/output operations in a process control comprising: a processor unit for fetching signals representative of states of object processes to be controlled and for operating upon them in accordance with a program stored in advance; a process input/output unit for fetching the state signals of the object processes to be controlled and for reading out results of the operation of the processor unit so as to provide output signals for controlling the object processes to be controlled; a random access buffer memory connected between the processor unit and the process input/output unit; timing signal generator means connected to said random access buffer memory for determining a first timing during which the processor unit may access the random access buffer memory and a second timing for the process input/output unit to access the random access buffer memory; and function selecting means connected to said processor unit for sending a selecting signal to the random access buffer memory in accordance with a write-in or read-out instruction; whereby the access to the random access buffer memory from the processor unit and that from the process input/output unit can be performed independent of each other.
Claim 6
Independent Claim
195 words
A system for controlling input/output operations in a process control comprising: a processor unit for fetching signals representative of states of object processes to be controlled and for operating upon them in accordance with a program stored in advance; a process input/output unit for fetching the state signals of the object processes to be controlled and for reading out results of the operation of the processor unit so as to provide output signals for controlling the object processes to be controlled; a random access buffer memory connected between the processor unit and the process input/output unit; timing signal generator means connected to said random access buffer memory for determining a first timing during which the processor unit may access the random access buffer memory and a second timing for the process input/output unit to access the random access buffer memory; and function selecting means connected to said processor unit for sending a selecting signal to the random access buffer memory in accordance with a write-in or read-out instruction; whereby the access to the random access buffer memory from the processor unit and that from the process input/output unit can be performed independent of each other.
Claim 7
Dependent Claim
61 words
A system for controlling input/output operations in a process control according to claim 4, wherein said timing signal generator means includes a signal generator circuit for producing first and second signals which alternate at a predetermined period corresponding to the sum of the access time to the random access buffer memory from the processor unit and from the process input/output unit.
Claim 8
Dependent Claim
69 words
A system for controlling input/output operations in a process control according to claim 4, wherein said random access buffer memory comprises, in respect of at least one object process to be controlled, an input data region for storing the state signal of the object process by way of the process input/output unit, and a controlled output data region for storing the result of the operation of the processor unit.
Claim 9
Dependent Claim
91 words
A system for controlling input/ouput operations in a process control according to claim 5, wherein said timing signal generator means further includes address counter means responsive to said signal generator circuit for generating sequential memory addresses by which said process input/output unit may access said random access buffer memory, and further including address selection means connected to said address counter means and said processor being responsive to said first and second signals for applying either said sequential memory address or random addresses from said processor to said random access buffer memory.
Claim 10
Dependent Claim
54 words
A system for controlling input/output operations in a process control according to claim 7, wherein said signal generator circuit includes a timing pulse generator for generating timing pulses without regard to the operation timing of said processor unit and frequency divider means responsive to said timing pulses for generating said first and second signals.
Claim 11
Dependent Claim
51 words
A system for controlling input/output operations in a process control according to claim 8, further including logic control means responsive to said first and second signals for controlling said address selecting means to permit alternate accessing of said random access buffer memory by said processor unit and said process input/output unit.
Claim 12
Dependent Claim
81 words
A system for controlling input/output operations in a process control according to claim 9, wherein said timing signal generator means includes means responsive to a strobe signal generated by said processor unit for generating a clock signal, said logic control means including means responsive to said clock signal during the buffer memory access time allocated to said processor unit by one of said first and second signals for applying the selecting signal from said function selecting means to said buffer memory.
Claim 13
Independent Claim
186 words
A system for controlling input/output operations in a process control comprising: a processor unit for fetching signals representative of states of object processes to be controlled and for operating upon them in accordance with a program stored in advance; a process input/output unit for fetching the state signals of the object processes to be controlled and for reading out results of the operation of the processor unit so as to provide output signals for controlling the object processes to be controlled; a random access buffer memory connected between the processor unit and the process input/output unit, first means for storing the state signals of the object processes in said buffer memory and then inputting said signals to said processor unit, and second means for storing the signals produced as the results of the operation of the processor unit on the basis of the inputted state signals in said buffer memory and then outputting said signals to the object processes to be controlled through said process input/output unit; and timing means for controlling said first and second means to operate alternately in successive periods of predetermined duration.
Claim 14
Independent Claim
186 words
A system for controlling input/output operations in a process control comprising: a processor unit for fetching signals representative of states of object processes to be controlled and for operating upon them in accordance with a program stored in advance; a process input/output unit for fetching the state signals of the object processes to be controlled and for reading out results of the operation of the processor unit so as to provide output signals for controlling the object processes to be controlled; a random access buffer memory connected between the processor unit and the process input/output unit, first means for storing the state signals of the object processes in said buffer memory and then inputting said signals to said processor unit, and second means for storing the signals produced as the results of the operation of the processor unit on the basis of the inputted state signals in said buffer memory and then outputting said signals to the object processes to be controlled through said process input/output unit; and timing means for controlling said first and second means to operate alternately in successive periods of predetermined duration.
Claim 15
Dependent Claim
48 words
A system for controlling input/output operations in a process control according to claim 11, further including control means for controlling said first and second means to effect access by said processor unit to said buffer memory asynchronously with access by said process input/output unit to said buffer memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-12 | 1986-01-11 | 1986-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-12 | 1990-01-11 | 1990-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-12 | 1994-01-11 | 1994-07-13 | $7700.00 | Window Closed / Lapsed |