US4675552A — Single input/multiple output logic interface circ…

Claim 1

Independent Claim 132 words

A logic circuit for generating a first output representative of a first prescribed logic level in response to a first prescribed input current and for generating a second output representative of a second prescribed logic level in response to a second prescribed input current comprising: an input terminal to which one of said first and second prescribed input currents may be applied; at least one output terminal from which one of said first and second outputs is provided; and means, coupled between said input and output terminals and having a voltage reference source, for establishing and maintaining the voltage level at said input terminal at the voltage provided by said voltage reference source irrespective of the application to said input terminal of either one of said first and second prescribed input currents.

Claim 2

Dependent Claim 132 words

A logic circuit for generating a first output representative of a first prescribed logic level in response to a first prescribed input current and for generating a second output representative of a second prescribed logic level in response to a second prescribed input current comprising: an input terminal to which one of said first and second prescribed input currents may be applied; at least one output terminal from which one of said first and second outputs is provided; and means, coupled between said input and output terminals and having a voltage reference source, for establishing and maintaining the voltage level at said input terminal at the voltage provided by said voltage reference source irrespective of the application to said input terminal of either one of said first and second prescribed input currents.

Claim 3

Dependent Claim 39 words

A logic circuit according to claim 1, wherein said means includes, as said voltage reference source, a plurality of bipolar transistors, the base-emitter junctions of which are effectively connected in series between a reference terminal and said input terminal.

Claim 4

Dependent Claim 61 words

A logic circuit according to claim 1, wherein said means includes a transistor circuit for providing a first current flow path between said input terminal and a reference terminal in response to said first prescribed input current and for providing a second current flow path between said input terminal and said reference terminal in response to said second prescribed input current.

Claim 5

Dependent Claim 53 words

A logic circuit according to claim 3, wherein said transistor circuit comprises a plurality of bipolar transistors connected between said input terminal and said reference terminal such that base-emitter junctions thereof are effectively connected in series between said input terminal and said reference terminal, said series-connected base-emitter junctions providing said voltage reference source.

Claim 6

Dependent Claim 73 words

A logic circuit according to claim 4, wherein said plurality of bipolar transistors comprises a first transistor, the base-emitter junction of which is connected in parallel with a first prescribed impedance for establishing the current through said impedance as part of said first current flow path in response to said first prescribed input current, and a second transistor, a base-emitter junction of which is coupled between said first impedance and said input terminal.

Claim 7

Dependent Claim 62 words

A logic circuit according to claim 5, wherein said second transistor has its base and collector connected to said input terminal, and wherein said transistor circuit further includes means for providing said second current flow path from said input terminal through the collector-emitter path of said first transistor in response to said second prescribed input current being applied to said input terminal.

Claim 8

Dependent Claim 87 words

A logic circuit according to claim 6, wherein said second transistor is a multi emitter transistor, a first emitter of which is coupled to said first impedance, and a second emitter of which is coupled to the collector of said first transistor so that said first current flow path is provided by way of the collector-first emitter path of said second transistor and said second current flow path is provided by the collector-second emitter path of said second transistor and the collector-emitter path of said first transistor.

Claim 9

Dependent Claim 27 words

A logic circuit according to claim 2, wherein said means includes an output bipolar transistor coupled in circuit between a voltage supply terminal and said input terminal.

Claim 10

Dependent Claim 46 words

A logic circuit according to claim 8, wherein said output transistor has its collector-emitter path coupled in series between said voltage supply terminal and said input terminal and its base coupled in circuit with means for providing a prescribed voltage offset relative to said reference terminal.

Claim 11

Dependent Claim 46 words

A logic circuit according to claim 9, further including means, coupled between said input terminal and said output transistor, for establishing a prescribed voltage level at the base of said output transistor in response to said first prescribed input current being applied to said input terminal.

Claim 12

Dependent Claim 49 words

A logic circuit according to claim 10, wherein said establishing means comprises means for providing a preselected voltage offset at the emitter of said output transistor relative to the voltage level at said input terminal in response to said first prescribed input current being applied to said input terminal.

Claim 13

Dependent Claim 44 words

A logic circuit according to claim 11, wherein said establishing means comprises a voltage offset resistor through which a prescribed current, as established by said voltage reference source, flows in response to the application of said first prescribed input current to said input terminal.

Claim 14

Dependent Claim 44 words

A logic circuit according to claim 12, wherein the magnitude of said preselected voltage offset is substantially greater than any differential in the voltage present at said input terminal as a result of the successive application of said first and second input currents thereto.

Claim 15

Dependent Claim 49 words

A logic circuit according to claim 9, wherein said prescribed voltage offset providing means comprises a voltage offset control bipolar transistor and a diode coupled in series between the base of said output transistor and the collector of one of said plurality of transistors of said voltage reference source.

Claim 16

Dependent Claim 63 words

A logic circuit according to claim 14, wherein said voltage offset control transistor has its collector-emitter path coupled between the base of said output transistor and said diode and its base coupled to a voltage divider circuit one end of which is coupled to a voltage supply terminal and the other end of which is coupled to the base of said output transistor.

Claim 17

Dependent Claim 79 words

A logic circuit according to claim 15, wherein said voltage divider circuit includes an impedance coupled between the base and collector of said voltage offset control transistor for providing, in response to the application of said second prescribed input current to said input terminal, a voltage drop thereacross that is substantially greater than any differential in the voltage present at said input terminal as a result of the successive application of said first and second prescribed input currents thereto.

Claim 18

Dependent Claim 39 words

A logic circuit according to claim 8, wherein said output bipolar transistor comprises a multi-emitter transistor, selected emitters of which are coupled to respective output terminals from each of which one of said first and second outputs are provided.

Claim 19

Dependent Claim 221 words

For use in a logic circuit having a plurality of logic devices interconnected with one another by signal interconnection links to perform at least one composite logical operation, a logic device to be incorporated into said logic circuit, as at least one of said logic devices, for effectively minimizing a voltage swing on an interconnection link to which said logic device is coupled, said logic device comprising: an input terminal, interconnected with said interconnection link, for receiving therefrom one of a first prescribed input current associated with a first prescribed logic state and a second prescribed input current associated with a second prescribed logic state; at least one output terminal from which said logic device provides a first output representative of said first prescribed logic state in response to said input terminal receiving said second prescribed input current, and a second output representative of said second prescribed logic state in response to said input terminal receiving said first prescribed input current; and means, coupled between said input and output terminals and having a voltage reference source, for establishing and maintaining the voltage level at said input terminal, and thereby on said interconnection link, at the voltage provided by said voltage reference source irrespective of the application to said input terminal of either one of said first and second prescribed input currents.

Claim 20

Dependent Claim 221 words

For use in a logic circuit having a plurality of logic devices interconnected with one another by signal interconnection links to perform at least one composite logical operation, a logic device to be incorporated into said logic circuit, as at least one of said logic devices, for effectively minimizing a voltage swing on an interconnection link to which said logic device is coupled, said logic device comprising: an input terminal, interconnected with said interconnection link, for receiving therefrom one of a first prescribed input current associated with a first prescribed logic state and a second prescribed input current associated with a second prescribed logic state; at least one output terminal from which said logic device provides a first output representative of said first prescribed logic state in response to said input terminal receiving said second prescribed input current, and a second output representative of said second prescribed logic state in response to said input terminal receiving said first prescribed input current; and means, coupled between said input and output terminals and having a voltage reference source, for establishing and maintaining the voltage level at said input terminal, and thereby on said interconnection link, at the voltage provided by said voltage reference source irrespective of the application to said input terminal of either one of said first and second prescribed input currents.

Claim 21

Dependent Claim 62 words

A logic device according to claim 18, further including means, coupled between said input and output terminals, for establishing a prescribed voltage differential within said device, between said first and second prescribed logic states, that is substantially greater than any voltage swing at said input terminal as a result of the successive application of said first and second prescribed input currents thereto.

Claim 22

Dependent Claim 24 words

A logic device according to claim 19, wherein said prescribed voltage differential is approximately an order of magnitude as great as said voltage swing.

Claim 23

Dependent Claim 40 words

A logic device according to claim 18, wherein said means includes, as said voltage reference source, a series connection of the base-emitter junctions of a plurality of bipolar transistors coupled in series between said input terminal and a reference terminal.

Claim 24

Dependent Claim 73 words

A logic device according to claim 21, wherein said plurality of transistors form a transistor circuit connected between said input terminal and said reference terminal so as to provide a first current flow path between said input terminal and said reference terminal in response to said first prescribed input current and provide a second current flow path between said input terminal and said reference terminal in response to said second prescribed input current.

Claim 25

Dependent Claim 72 words

A logic device according to claim 22, wherein said plurality of transistors comprises a first transistor, the base-emitter junction of which is connected in parallel with a first prescribed impedance for establishing the current through said impedance as part of said first current flow path in response to said first prescribed input current, and a second transistor, a base-emitter junction of which is coupled between said first impedance and said input terminal.

Claim 26

Dependent Claim 62 words

A logic device according to claim 23, wherein said second transistor has its base and collector connected to said input terminal, and wherein said transistor circuit further includes means for providing said second current flow path from said input terminal through the collector-emitter path of said first transistor in response to said second prescribed input current being applied to said input terminal.

Claim 27

Dependent Claim 86 words

A logic device according to claim 24, wherein said second transistor is a multi-emitter transistor, a first emitter of which is coupled to said first impedance, and a second emitter of which is coupled to the collector of said first transistor so that said first current flow path is provided by way of the collector-first emitter path of said second transistor and said second current flow path is provided by the collector-second emitter path of said second transistor and the collector-emitter path of said first transistor.

Claim 28

Dependent Claim 27 words

A logic device according to claim 21, wherein said means includes an output bipolar transistor coupled in circuit between a voltage supply terminal and said input terminal.

Claim 29

Dependent Claim 45 words

A logic device according to claim 26, wherein said output transistor has its collector-emitter path coupled in series between said voltage supply terminal and said input-terminal and its base coupled in circuit with means for providing a prescribed voltage offset relative to said reference terminal.

Claim 30

Dependent Claim 49 words

A logic device according to claim 27, wherein said prescribed voltage offset providing means comprises a voltage offset control bipolar transistor and a diode coupled in series between the base of said output transistor and the collector of one of said plurality of transistors of said voltage reference source.

Claim 31

Dependent Claim 63 words

A logic device according to claim 28, wherein said voltage offset control transistor has its collector-emitter path coupled between the base of said output transistor and said diode and its base coupled to a voltage divider circuit one end of which is coupled to a voltage supply terminal and the other end of which is coupled to the base of said output transistor.

Claim 32

Dependent Claim 38 words

A logic device according to claim 26, wherein said output transistor comprises a multi-emitter transistor, selected emitters of which are coupled to respective output terminals from each of which one of said first and second outputs are provided.

Claim 33

Dependent Claim 46 words

A logic device according to claim 27, further including means, coupled between said input terminal and said output transistor, for establishing a prescribed voltage level at the base of said output transistor in response to said first prescribed input current being applied to said input terminal.

Claim 34

Dependent Claim 49 words

A logic device according to claim 31, wherein said establishing means comprises means for providing a preselected voltage offset at the emitter of said output transistor relative to the voltage level at said input terminal in response to said first prescribed input current being applied to said input terminal.

Claim 35

Dependent Claim 44 words

A logic device according to claim 32, wherein said establishing means comprises a voltage offset resistor through which a prescribed current, as established by said voltage reference source, flows in response to the application of said first prescribed input current to said input terminal.

Claim 36

Dependent Claim 44 words

A logic device according to claim 33, wherein the magnitude of said preselected voltage offset is substantially greater than any differential in the voltage present at said input terminal as a result of the successive application of said first and second input currents thereto.

Claim 37

Dependent Claim 243 words

For use with a logic circuit having a plurality of logic devices interconnected with one another by signal interconnection links so as to perform at least one composite logical operation, at least one of said logic devices having an input terminal coupled to an interconnection link for receiving therefrom one of a first prescribed input current associated with a first prescribed logic state and a second prescribed input current associated with a second prescribed logic state, and at least one output terminal from which said logic device provides a first output representative of said first prescribed logic state in response to said input terminal receiving said second prescribed input current, and a second output representative of said second prescribed logic state in response to said input terminal receiving said first prescribed input current, a method of effectively minimizing a voltage swing on said interconnection link and thereby increasing the speed at which capacitance associated with said interconnection link is charged and discharged in the course of transitions between said first and second logic states, said method comprising the steps of: applying to said interconnection link a voltage level corresponding to the voltage provided by a voltage reference source coupled to said input terminal; and maintaining the voltage level on said interconnection link at the voltage provided by a voltage reference source coupled to said input terminal irrespective of which of said first and second prescribed input currents is applied to said input terminal.

Claim 38

Dependent Claim 243 words

For use with a logic circuit having a plurality of logic devices interconnected with one another by signal interconnection links so as to perform at least one composite logical operation, at least one of said logic devices having an input terminal coupled to an interconnection link for receiving therefrom one of a first prescribed input current associated with a first prescribed logic state and a second prescribed input current associated with a second prescribed logic state, and at least one output terminal from which said logic device provides a first output representative of said first prescribed logic state in response to said input terminal receiving said second prescribed input current, and a second output representative of said second prescribed logic state in response to said input terminal receiving said first prescribed input current, a method of effectively minimizing a voltage swing on said interconnection link and thereby increasing the speed at which capacitance associated with said interconnection link is charged and discharged in the course of transitions between said first and second logic states, said method comprising the steps of: applying to said interconnection link a voltage level corresponding to the voltage provided by a voltage reference source coupled to said input terminal; and maintaining the voltage level on said interconnection link at the voltage provided by a voltage reference source coupled to said input terminal irrespective of which of said first and second prescribed input currents is applied to said input terminal.

Claim 39

Dependent Claim 55 words

A method according to claim 35, further including the step of establishing a prescribed voltage differential within said device, between said first and second prescribed logic states, that is substantially greater than any voltage swing at said input terminal as a result of the successive application thereto of said first and second prescribed input currents.

Claim 40

Dependent Claim 23 words

A method according to claim 36, wherein said prescribed voltage differential is approximately an order of magnitude as great as said voltage swing.

Claim 41

Dependent Claim 43 words

A method according to claim 35, wherein said voltage reference source is provided by the sum of the forward base-emitter voltage drops across the base-emitter junctions of a plurality of bipolar transistors coupled in series between said input terminal and said reference terminal.

Claim 42

Dependent Claim 72 words

A method according to claim 38, wherein said plurality of transistors form a transistor circuit connected between said input terminal and said reference terminal so as to provide a first current flow path between said input terminal and said reference terminal in response to said first prescribed input current and provide a second current flow path between said input terminal and said reference terminal in response to said second prescribed input current.

Claim 43

Dependent Claim 71 words

A method according to claim 39, wherein said plurality of transistors comprises a first transistor, the base-emitter junction of which is connected in parallel with a first prescribed impedance for establishing the current through said impedance as part of said first current flow path in response to said first prescribed input current, and a second transistor, a base-emitter junction of which is coupled between said first impedance and said input terminal.

Claim 44

Dependent Claim 61 words

A method according to claim 40, wherein said second transistor has its base and collector connected to said input terminal, and wherein said transistor circuit further includes means for providing said second current flow path from said input terminal through the collector-emitter path of said first transistor in response to said second prescribed input current being applied to said input terminal.

Claim 45

Dependent Claim 85 words

A method according to claim 41, wherein said second transistor is a multi-emitter transistor, a first emitter of which is coupled to said first impedance, and a second emitter of which is coupled to the collector of said first transistor so that said first current flow path is provided by way of the collector-first emitter path of said second transistor and said second current flow path is provided by the collector-second emitter path of said second transistor and the collector-emitter path of said first transistor.

Claim 46

Dependent Claim 27 words

A method according to claim 42, wherein said logic device includes an output bipolar transistor coupled in circuit between a voltage supply terminal and said input terminal.

Claim 47

Dependent Claim 40 words

A method according to claim 43, wherein said output transistor has its collector-emitter path coupled in series between said voltage supply terminal and said input-terminal and its base coupled to receive a prescribed voltage offset relative to said reference terminal.

Claim 48

Dependent Claim 37 words

A method according to claim 44, further including the step of establishing a prescribed voltage level at the base of said output transistor in response to said first prescribed input current being applied to said input terminal.

Claim 49

Dependent Claim 49 words

A method according to claim 45, wherein said establishing step comprises the step of providing a preselected voltage offset at the emitter of said output transistor relative to the voltage level at said input terminal in response to said first prescribed input current being applied to said input terminal.

Claim 50

Dependent Claim 43 words

A method according to claim 46, wherein the magnitude of said preselected voltage offset is substantially greater than any differential in the voltage present at said input terminal as a result of the successive application of said first and second input currents thereto.

Claim 51

Dependent Claim 52 words

A method according to claim 44, wherein said prescribed voltage offset is generated by the step of coupling a voltage offset control bipolar transistor and a diode coupled in series between the base of said output transistor and the collector of one of said plurality of transistors of said voltage reference source.

Claim 52

Dependent Claim 62 words

A method according to claim 48, wherein said voltage offset control transistor has its collector-emitter path coupled between the base of said output transistor and said diode and its base coupled to a voltage divider circuit one end of which is coupled to a voltage supply terminal and the other end of which is coupled to the base of said output transistor.

Claim 53

Dependent Claim 76 words

A method according to claim 49, wherein said voltage circuit includes an impedance coupled between the base and collector of said voltage offset control transistor for providing, in response to the application of said prescribed input current to said input terminal, a voltage drop thereacross that is substantially greater than any differential in the voltage present on said interconnection link as a result of the successive application of said first and second prescribed input currents thereto.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1990-06-22	1990-12-22	1991-06-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1994-06-22	1994-12-22	1995-06-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1998-06-22	1998-12-22	1999-06-23	$7700.00	Window Closed / Lapsed

Single input/multiple output logic interface circuit having minimized voltage swing

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag