US4228371A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit
Assignee: RCA Corp
•
Filing: 1977-12-05
•
Granted: 1980-10-14
•
Expires: 1997-12-05
Abstract
Abstract A logic circuit in which a phase splitting transistor is connected at its emitter to the base of an output pull-down transistor having a bypass network connected between its base and emitter. The bypass network, comprised of a resistor in series with a Schottky diode, enables the phase splitting transistor to be turned on and off prior to the corresponding turn-on and turn-off of the pull-down transistor, provides a path for discharging the base of the pull-down transistor and for passing its collector-to-base leakage, and compensates for temperature variations of the pull-down transistor to maintain the propagation delay of the logic circuit relatively constant over a wide temperature range.
Inventors
- 👤 James D. Mazgy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03K19/0008; H03K19/001; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
265 words
The combination comprising: an input point for the application thereto of an input signal; an output point for producing thereat an output signal responsive to said input signal; first and second power terminals for the application therebetween of an operating potential; first and second transistors, each transistor having a base, an emitter and a collector; means connected between said input point and the base of said first transistor for coupling the input signal to the base of said first transistor; means connecting the collector of said first transistor to said first power terminal; means connecting the base of said second transistor to the emitter of said first transistor, the collector of said second transistor to said output point, and the emitter of said second transistor to said second power terminal; a resistor and a Schottky barrier diode; said diode characterized in that its forward drop is substantially greater than zero volts but less than the base-to-emitter forward drop (V BE ) of said second transistor and in that said diode has a larger rectifying area than the area of the base-to-emitter junction of said second transistor; and negligible impedance means connecting said resistor and said diode in series between the base and emitter of said second transistor; said Schottky barrier diode being poled to conduct current in the same forward direction as the base-to-emitter junction of said second transistor for enabling current flow through the diode prior to the flow of current through the base-to-emitter junction of the second transistor in response to a forward biasing signal applied to the base of said second transistor.
Claim 2
Dependent Claim
265 words
The combination comprising: an input point for the application thereto of an input signal; an output point for producing thereat an output signal responsive to said input signal; first and second power terminals for the application therebetween of an operating potential; first and second transistors, each transistor having a base, an emitter and a collector; means connected between said input point and the base of said first transistor for coupling the input signal to the base of said first transistor; means connecting the collector of said first transistor to said first power terminal; means connecting the base of said second transistor to the emitter of said first transistor, the collector of said second transistor to said output point, and the emitter of said second transistor to said second power terminal; a resistor and a Schottky barrier diode; said diode characterized in that its forward drop is substantially greater than zero volts but less than the base-to-emitter forward drop (V BE ) of said second transistor and in that said diode has a larger rectifying area than the area of the base-to-emitter junction of said second transistor; and negligible impedance means connecting said resistor and said diode in series between the base and emitter of said second transistor; said Schottky barrier diode being poled to conduct current in the same forward direction as the base-to-emitter junction of said second transistor for enabling current flow through the diode prior to the flow of current through the base-to-emitter junction of the second transistor in response to a forward biasing signal applied to the base of said second transistor.
Claim 3
Dependent Claim
40 words
The combination as claimed in claim 1 further including a third transistor connected at its base to the collector of said first transistor; and means connecting its collector to said first power terminal, and its emitter to said output point.
Claim 4
Dependent Claim
36 words
The combination as claimed in claim 2 wherein the forward drop (V FS ) of said Schottky barrier diode is less than the V BE of said second transistor for the same value of current therethrough.
Claim 5
Dependent Claim
18 words
The combination as claimed in claim 3 wherein said first, second and third transistors are Schottky clamped transistors.
Claim 6
Dependent Claim
52 words
The combination as claimed in claim 3 wherein said first transistor is turned-on when the potential at its base is equal to V BE plus V FS , and wherein said second transistor is turned on when the potential at the base of said first transistor is equal to 2V BE .
References Cited (Backward Citations)
US3751680A
Cited
US3836789A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-14 | 1984-04-14 | 1984-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-14 | 1988-04-14 | 1988-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-14 | 1992-04-14 | 1992-10-14 | $7700.00 | Window Closed / Lapsed |