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US4673980A
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Video-signal time-axis correction apparatus
Assignee: NIPPON HOSO HYOKAI
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Filing: 1986-05-22
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Granted: 1987-06-16
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Expires: 2006-05-22
Abstract
Abstract A time-axis of a digital video-signal is converted to a standard time-axis by changing a clock signal contained therein to a standard clock signal and by locking phases of input synchronizing signals contained therein onto the phase of the standard clock signal through a memory for alternately writing and reading the digital video signal at one half of the period of the standard clock signal. As a result, the time-axis correction of the digital video signal is efficiently effected through the memory having a small capacity and a simplified controlling arrangement.
Inventors
- 👤 Keinosuke Murakami
- 👤 Kazumasa Enami
- 👤 Nobuyuki Yagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:39
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
367 words
A video-signal time-axis correction apparatus for converting an input time-axis based on an input video signal to a standard time-axis by changing an input clock signal indicating the input time-axis to a standard clock signal indicating the standard time-axis, comprising an analog to digital converting means for converting an input analog video-signal to an input digital video-signal under the control of said input clock signal, a synchronizing signal separating means for separating input synchronizing signals from said input analog video-signal and generating said input clock signal on the basis of said input synchronizing signals, a synchronizing signal reproducing means for generating said standard clock signal from standard synchronizing signals externally supplied on the basis of said standard time-axis, a clock converting means for converting said input synchronizing signals derived from said synchronizing signal separating means to output synchronizing signals being in phase with said standard clock signal derived from said synchronizing signal reproducing means, a memory means for memorizing said input digital video signal obtained in said analog to digital converting means, a writing address generating means for generating writing addresses for controlling the writing of digits of said input digital video signal into said memory means under the control of said standard clock signal derived from said synchronizing signal reproducing means and said output synchronizing signals derived from said clock converting means, a reading address generating means for generating reading addresses for controlling the reading of said digits from said memory means under the control of said standard clock signal and said standard synchronizing signals derived from said synchronizing signal reproducing means, a memory address generating means for generating memory addresses for alternately controlling the writing and the reading of said digits in said memory means for alternately switching said writing addresses and said reading addresses at one half of the period of said standard clock signal, so as to convert said input digital video signal to an output digital video signal, and a digital to analog converting means for converting said output digital video-signal derived from said memory means to an output analog video signal based on said standard time-axis under the control of said standard clock signal derived from said synchronizing signal reproducing means.
Claim 2
Dependent Claim
367 words
A video-signal time-axis correction apparatus for converting an input time-axis based on an input video signal to a standard time-axis by changing an input clock signal indicating the input time-axis to a standard clock signal indicating the standard time-axis, comprising an analog to digital converting means for converting an input analog video-signal to an input digital video-signal under the control of said input clock signal, a synchronizing signal separating means for separating input synchronizing signals from said input analog video-signal and generating said input clock signal on the basis of said input synchronizing signals, a synchronizing signal reproducing means for generating said standard clock signal from standard synchronizing signals externally supplied on the basis of said standard time-axis, a clock converting means for converting said input synchronizing signals derived from said synchronizing signal separating means to output synchronizing signals being in phase with said standard clock signal derived from said synchronizing signal reproducing means, a memory means for memorizing said input digital video signal obtained in said analog to digital converting means, a writing address generating means for generating writing addresses for controlling the writing of digits of said input digital video signal into said memory means under the control of said standard clock signal derived from said synchronizing signal reproducing means and said output synchronizing signals derived from said clock converting means, a reading address generating means for generating reading addresses for controlling the reading of said digits from said memory means under the control of said standard clock signal and said standard synchronizing signals derived from said synchronizing signal reproducing means, a memory address generating means for generating memory addresses for alternately controlling the writing and the reading of said digits in said memory means for alternately switching said writing addresses and said reading addresses at one half of the period of said standard clock signal, so as to convert said input digital video signal to an output digital video signal, and a digital to analog converting means for converting said output digital video-signal derived from said memory means to an output analog video signal based on said standard time-axis under the control of said standard clock signal derived from said synchronizing signal reproducing means.
Claim 3
Dependent Claim
46 words
A video-signal time-axis correction apparatus as claimed in claim 1, wherein said input digital video signal is supplied to said memory means through said clock converting means in which said input clock signal contained in said input digital video-signal is converted to said standard clock signal.
Claim 4
Dependent Claim
97 words
A video-signal time-axis correction apparatus as claimed in claim 2, wherein said clock converting means comprises two one-line memory means for being alternately used for alternately writing-in and reading-out said input digital video signal, a first counting means for counting said input clock signal at the period of the input line synchronizing signal, so as to control the writing-in of said two one-line memory means, and a second counting means for counting said standard clock signal at the period of the input line synchronizing signal, so as to control the reading-out of said two one-line memory means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-15 | 1990-12-15 | 1991-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-15 | 1994-12-15 | 1995-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-15 | 1998-12-15 | 1999-06-16 | $7700.00 | Window Closed / Lapsed |