US4673968A
Expired / Lapsed
US
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Integrated MOS transistors having a gate metallization composed of tantalum or niobium or their silicides
Assignee: Siemens AG
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Filing: 1986-05-27
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Granted: 1987-06-16
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Expires: 2006-05-27
Abstract
Abstract Chemical reactions between a tantalum or tantalum silicide metallization layer and an underlying thin gate oxide are avoided by the interposition of an intermediate layer of oxygen-doped tantalum or tantalum silicide whose thickness amounts to about 1/20 to 1/5 of the layer thickness of the entire gate metallization. The metallization layer is produced by high-frequency sputtering in which oxygen is added at the beginning of the process and argon is used as a sputtering gas. Low specific resistance values are accomplished by means of this gate metallization.
Inventors
- 👤 Konrad Hieber
- 👤 Franz Neppl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:43
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316; H10D64/01318; H10D64/0132; H10D64/665; H10D64/668; H10D64/669; H10P; H10P14/00; H10P14/40; H10P14/412
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
68 words
An integrated MOS transistor comprising: a silicon substrate, a gate oxide layer overlying said substrate, and a gate metallization over said gate oxide layer including a tantalum or niobium metal or a tantalum or niobium silicide, said gate metallization including an intermediate layer of an oxygen doped metal or metal silicide layer having a thickness of from 1/20 to 1/5 of the overall thickness of the gate metallization.
Claim 2
Dependent Claim
68 words
An integrated MOS transistor comprising: a silicon substrate, a gate oxide layer overlying said substrate, and a gate metallization over said gate oxide layer including a tantalum or niobium metal or a tantalum or niobium silicide, said gate metallization including an intermediate layer of an oxygen doped metal or metal silicide layer having a thickness of from 1/20 to 1/5 of the overall thickness of the gate metallization.
Claim 3
Dependent Claim
24 words
An integrated MOS transistor according to claim 1 wherein the thickness of said intermediate layer is in the range from 5 to 100 nm.
Claim 4
Dependent Claim
28 words
An integrated MOS transistor according to claim 1 wherein said gate metallization includes an intermediate layer of oxygen-doped Ta silicide and a 400 to 500 nm thick tantalum
Claim 5
Dependent Claim
33 words
An integrated MOS circuit according to claim 1 wherein said intermediate layer is composed of an amorphous tantalum sub-oxide or tantalum silicide whose tantalum content is in the form of an amorphous sub-oxide.
Claim 6
Dependent Claim
19 words
An integrated MOS circuit according to claim 1 wherein said gate metallization is produced by high frequency cathode sputtering.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-15 | 1990-12-15 | 1991-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-15 | 1994-12-15 | 1995-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-15 | 1998-12-15 | 1999-06-16 | $7700.00 | Window Closed / Lapsed |