Clock signal reproducing circuit for a player reproducing information of a disc

Claim 2

A clock signal reproducing circuit in a player reproducing information of a digital disc comprising: an input signal terminal receiving an input signal reproduced from the disc via pickup means; clock signal generating circuit means including a voltage controlled oscillator for generating a clock signal having a period of about 1/n (n being an integer) of the input signal reproduced from said pickup means which has been applied to said input signal terminal, said voltage controlled oscillator having a positive first control voltage applied to it corresponding to the actual period; an output signal terminal from which the clock signal generated by said voltage controlled oscillator is delivered; first detecting circuit means, receiving the input signal reproduced from said pickup means and the clock signal gneerated by said voltage controlled oscillator, for detecting a phase error between the two signals to deliver out a first detection signal, said first detection signal containing the phase error and a component equal to 1/2 period of the clock signal generated by siad voltage controlled oscillator; second detecting circuit means receiving the clock signal generated by said voltage controlled oscillator for generating the component equal to 1/2 period of the clock signal as a second detection signal each time a first detection signal is generated; and combining circuit means receiving the first and second detection signals for cancelling the component equal to 1/2 period of the clock signal contained in the first and second detection signals and delivering out only the phase error component contained in the first detection signal as a bipolar second control voltage, wherein the second control voltage is applied to the voltage controlled oscillator in addition to the first control voltage so that the clock signal generated by said clock signal generating circuit means is in phase with the input signal applied to said input signal terminal.

Claim 3

A clock signal reproducing circuit as defined in claim 1 wherein said clock signal generating circuit means further comprises a clock detecting circuit for detecting a clock signal from the input signal reproduced from said pickup means and a frequency-voltage converter for converting the clock signal detected by said clock signal detecting circuit into a voltage corresponding to its frequency, wherein the output of the converter is the first control voltage.

Claim 4

A clock signal reproducing circuit as defined in claim 1 wherein said first detecting circuit means comprises a first D-flip-flop circuit receiving the input signal reproduced from said pickup means and the clock signal generated by said voltage controlled oscillator, a first exclusive OR gate receiving the input signal reproduced from said pickup means and a Q output of said first D-flip-flop circuit and a time constant circuit coupled to the output of said first exclusive OR gate.

Claim 5

A clock signal reproducing circuit as defined in claim 1 wherein said second detecting circuit means comprises an inverter receiving the clock signal generated by said clock signal generating means, a second D-flip-flop circuit receiving an output signal of said inverter and the Q output of said first D-flip-flop circuit, a second exclusive OR gate receiving the Q outputs of said first and second D-flip-flop circuits and a time constant circuit coupled to the output of said second exclusive OR gate.

Claim 6

A clock circuit reproducing circuit as defined in claim 1 wherein said combining circuit means is a subtractor circuit.

Claim 7

A clock signal reproducing circuit in a player reproducing information of a digital disc comprising: an input signal terminal receiving an input signal reproduced from the disc via pickup menas; clock signal generating circuit means for generating a clock signal having a period of about 1/n (n being an integer) of the input signal reproduced from said pickup means which has been applied to said input signal terminal, wherein said clock signal generating circuit means comprises a clock detecting circuit for detecting a clock signal from the input signal reproduced from said pickup means, a frequency-voltage converter for converting the clock signal detected by said clock signal detecting circuit into a voltage corresponding to its frequency and a voltage-controlled oscillator driven by this voltage to provide said clock signal having a period of about 1/n; an output signal terminal from which the clock signal generated by said clock signal generating circuit means is delivered; first detecting circuit means, receiving the input signal reproduced from said pickup means and the clock signal gnerated by said clock signal generating circuit means, for detecting a phase error between the two received signals to deliver out the phase error as a first detection signal, said first detection signal containing a component equal to 1/2 period of the clock signal generated by said clock signal generating circuit means; second detecting circuit means receiving the clock signal generated by said clock signal generating circuit means for generating a component equal to 1/2 period of the clock signal as a second detection signal each time a first detection signal is generated; combining circuit means receiving the first and second detection signals for cancelling the component equal to 1/2 period of the clock signal contained in the first and second detection signals and delivering out only the phase error component contained in the first detection signal; and a phase locked loop operating in response to the phase error component delivered from said combinating circuit means in such a manner that the clock signal generated by said clock signal generating circuit means is in phase with the input signal applied to said input signal terminal.

Claim 8

A clock signal reproducing circuit in a player reproducing information of a digital disc comprising: an input signal terminal receiving an input signal reproduced from the disc via pickup menas; clock signal generating circuit means for generating a clock signal having a period of about 1/n (n being an integer) of the input signal reproduced from said pickup means which has been applied to said input signal terminal, wherein said clock signal generating circuit means comprises a clock detecting circuit for detecting a clock signal from the input signal reproduced from said pickup means, a frequency-voltage converter for converting the clock signal detected by said clock signal detecting circuit into a voltage corresponding to its frequency and a voltage-controlled oscillator driven by this voltage to provide said clock signal having a period of about 1/n; an output signal terminal from which the clock signal generated by said clock signal generating circuit means is delivered; first detecting circuit means, receiving the input signal reproduced from said pickup means and the clock signal gnerated by said clock signal generating circuit means, for detecting a phase error between the two received signals to deliver out the phase error as a first detection signal, said first detection signal containing a component equal to 1/2 period of the clock signal generated by said clock signal generating circuit means; second detecting circuit means receiving the clock signal generated by said clock signal generating circuit means for generating a component equal to 1/2 period of the clock signal as a second detection signal each time a first detection signal is generated; combining circuit means receiving the first and second detection signals for cancelling the component equal to 1/2 period of the clock signal contained in the first and second detection signals and delivering out only the phase error component contained in the first detection signal; and a phase locked loop operating in response to the phase error component delivered from said combinating circuit means in such a manner that the clock signal generated by said clock signal generating circuit means is in phase with the input signal applied to said input signal terminal.

Claim 9

A clock signal reproducing circuit for a digital disc player, comprising: clock detecting means for receiving an input signal reproduced from a digital disc and providing a positive first control voltage signal corresponding to the frequency of a disc clock signal contained in the input signal; a voltage controlled oscillator driven by the first control voltage to provide a system clock signal; first detector means for receiving the input signal and the system clock signal and providing a first detection signal including a component corresponding to the phase error between the signals and a component equal to one half of the period of the system clock signal; second detection means for receiving the system clock signal and providing a second detection signal, corresponding to each first detection signal, equal to oen half of the period of the system clock signal; and combining means for combining the first and second detection signals and providing a bipolar second control voltage representative of only the phase error, wherein the second control voltage is applied to the voltage controlled oscillator to increase or decrease the frequency thereof to eliminate said phase error.

Claim 10

A clock signal reproducing circuit for a digital disc player, comprising: clock detecting means for receiving an input signal reproduced from a digital disc and providing a positive first control voltage signal corresponding to the frequency of a disc clock signal contained in the input signal; a voltage controlled oscillator driven by the first control voltage to provide a system clock signal; first detector means for receiving the input signal and the system clock signal and providing a first detection signal including a component corresponding to the phase error between the signals and a component equal to one half of the period of the system clock signal; second detection means for receiving the system clock signal and providing a second detection signal, corresponding to each first detection signal, equal to oen half of the period of the system clock signal; and combining means for combining the first and second detection signals and providing a bipolar second control voltage representative of only the phase error, wherein the second control voltage is applied to the voltage controlled oscillator to increase or decrease the frequency thereof to eliminate said phase error.