US4672586A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory having circuit effecting refresh on variable cycles
Assignee: Hitachi Ltd
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Filing: 1984-06-06
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Granted: 1987-06-09
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Expires: 2004-06-06
Abstract
Abstract A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.
Inventors
- 👤 Katsuhiro Shimohigashi
- 👤 Masaharu Kubo
- 👤 Katsuki Miyauchi
- 👤 Toshiaki Masuhara
- 👤 Osamu Minato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4072; G11C11/4074; G11C5/00; G11C5/14; G11C5/141
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
82 words
A memory comprising: a memory device; a voltage generating circuit for converting a power source voltage supplied from an external device for reading and writing said memory device and supply operation power to said memory device, and generating a substrate bias voltage; a first battery for supplying said substrate bias voltage when the operation power is not supplied from said external device; and a second battery for supplying said memory device when the operation power is not supplied from said external device.
Claim 2
Dependent Claim
82 words
A memory comprising: a memory device; a voltage generating circuit for converting a power source voltage supplied from an external device for reading and writing said memory device and supply operation power to said memory device, and generating a substrate bias voltage; a first battery for supplying said substrate bias voltage when the operation power is not supplied from said external device; and a second battery for supplying said memory device when the operation power is not supplied from said external device.
Claim 3
Dependent Claim
32 words
A memory according to claim 3, wherein said memory further comprises a first capacitor connected in parallel with said first battery, and a second capacitor connected in parallel with said second battery.
Claim 4
Dependent Claim
16 words
A memory according to claim 2, wherein said memory device comprises a plurality of memory chips.
Claim 5
Dependent Claim
22 words
A memory according to claim 1, wherein said substrate bias voltage of said memory device is the grounding voltage of said battery.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-08 | 1990-12-08 | 1991-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-08 | 1994-12-08 | 1995-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-08 | 1998-12-08 | 1999-06-09 | $7700.00 | Window Closed / Lapsed |