CMOS integrated circuit

Claim 2

A CMOS integrated circuit comprising: a semiconductor substrate of a first type of conductivity; an impurity region of a second type of conductivity which is formed in said semiconductor substrate; a first MOS transistor formed in said substrate; a second MOS transistor formed in said impurity region; a power supply means for supplying a voltage to said first and second transistors; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply means; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and at least one resistor formed between said first and second contact regions in at least one of said substrate and said impurity region at a position below at least one of said first and second transistors, said resistor being electrically inserted between said power supply means and at least one of said first and second transistors.

Claim 3

A CMOS integrated circuit as recited in claim 1, wherein said semiconductor substrate is of an N type, and said impurity region is of a P type, and said first MOS transistor is of a P-channel type, and said second MOS transistor is of an N-channel type.

Claim 4

A CMOS integrated circuit as recited in claim 1, wherein said semiconductor substrate is of a P type, and said impurity region is of an N type, and said first MOS transistor is of an N-channel type, and said second MOS transistor is of a P-channel type.

Claim 5

A CMOS integrated circuit as recited in claim 1, wherein said power supply means includes a power supply line and a ground line, and said power supply line is connected to said first MOS transistor through said resistor.

Claim 6

A CMOS integrated circuit as recited in claim 1, wherein said power supply means includes a power supply line and a ground line, and said ground line is connected to said second MOS transistor through said resistor.

Claim 7

A CMOS integrated circuit as recited in claim 1, wherein said power supply means includes a power supply line and a ground line, and said power supply line is connected to said first MOS transistor through a first resistor, and said ground line is connected to said second MOS transistor through a second resistor.

Claim 8

A CMOS integrated circuit as recited in claim 1, wherein said resistor is formed by use of a part of at least one of said substrate and said impurity region.

Claim 9

A CMOS integrated circuit as recited in claim 1, wherein said first and second MOS transistors form a complementary circuit.

Claim 10

A CMOS integrated circuit comprising: a semiconductor substrate of a first type of conductivity which is formed in said semiconductor substrate; a CMOS circuit including a first MOS transistor which is formed in said substrate and a second MOS transistor which is formed in said impurity region; and a power supply means for supplying a voltage to said CMOS circuit, said power supply means being electrically connected to said CMOS circuit through a part of at least one of said substrate and said impurity region; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply means; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein said part of at least one of said substrate and said impurity region disposed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 11

A CMOS integrated circuit comprising: a semiconductor substrate of a first type of conductivity which is formed in said semiconductor substrate; a CMOS circuit including a first MOS transistor which is formed in said substrate and a second MOS transistor which is formed in said impurity region; and a power supply means for supplying a voltage to said CMOS circuit, said power supply means being electrically connected to said CMOS circuit through a part of at least one of said substrate and said impurity region; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply means; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein said part of at least one of said substrate and said impurity region disposed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 12

A CMOS integrated circuit as recited in claim 9, wherein said semiconductor substrate is of a P type, and said impurity region is an N well formed in said P type substrate, and said power supply means is electrically connected to said second MOS transistor through a part of said N well.

Claim 13

A CMOS integrated circuit as recited in claim 9, wherein said power supply means is electrically connected to said first MOS transistor through a part of said semiconductor substrate.

Claim 14

A CMOS integrated circuit comprising: a P type silicon substrate; an N well formed in said substrate; a CMOS circuit including an N channel type MOS transistor which is formed in said substrate and a P channel type MOS transistor which is formed in said N well; a power supply line to which a voltage is applied; a terminal electrode formed in said N well away from said CMOS circuit portion, said electrode being electrically connected to said power supply line; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply line; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein a part of said N well located between said CMOS circuit portion and terminal electrode disposed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 15

A CMOS integrated circuit comprising: a P type silicon substrate; an N well formed in said substrate; a CMOS circuit including an N channel type MOS transistor which is formed in said substrate and a P channel type MOS transistor which is formed in said N well; a power supply line to which a voltage is applied; a terminal electrode formed in said N well away from said CMOS circuit portion, said electrode being electrically connected to said power supply line; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply line; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein a part of said N well located between said CMOS circuit portion and terminal electrode disposed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 16

A CMOS integrated circuit as recited in claim 12, further comprising an external resistor which is electrically inserted between said CMOS circuit and ground.

Claim 17

A CMOS integrated circuit comprising: an N type silicon substrate; a P well formed in said substrate; a CMOS circuit including a P channel type MOS transistor which is formed in said substrate and an N channel type MOS transistor which is formed in said P well; a power supply line to which a voltage is applied; a first terminal electrode formed in said substrate away from said CMOS circuit portion, said first electrode being electrically connected to said power supply line; a second terminal electrode formed in said P well away from said CMOS circuit portion, said second terminal electrode being electrically connected to ground; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply line; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein a part of said substrate formed between said first and second contact regions and located between said first terminal electrode and CMOS circuit portion, and a part of said P well formed bwteen said first and second contact regions and located between said CMOS circuit portion and second terminal electrode function as resistors for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 18

A CMOS integrated circuit comprising: an N type silicon substrate; a P well formed in said substrate; a CMOS circuit including a P channel type MOS transistor which is formed in said substrate and an N channel type MOS transistor which is formed in said P well; a power supply line to which a voltage is applied; a first terminal electrode formed in said substrate away from said CMOS circuit portion, said first electrode being electrically connected to said power supply line; a second terminal electrode formed in said P well away from said CMOS circuit portion, said second terminal electrode being electrically connected to ground; a first contact region disposed in at least one of said substrate and said impurity region, said first contact region being connected to said power supply line; a second contact region disposed opposite to said first contact region via at least one of said first and second MOS transistors in at least one of said substrate and said impurity region, said second contact region being connected to at least one of said first and second MOS transistors; and wherein a part of said substrate formed between said first and second contact regions and located between said first terminal electrode and CMOS circuit portion, and a part of said P well formed bwteen said first and second contact regions and located between said CMOS circuit portion and second terminal electrode function as resistors for thereby preventing an occurrence of a latch-up phenomenon of said CMOS integrated circuit.

Claim 19

A semiconductor memory device comprising: a semiconductor substrate and an impurity region, said substrate and region being of opposite conductivities; a plurality of memory cells which are comprised of a CMOS structure and formed in said substrate; and a power supply line for supplying a voltage to said memory cells, said power supply line being formed at a position away from said memory cells and electrically connected to said memory cells through a portion of said substrate which is located below said memory cells; a first contact region disposed in at least one of said substrates and said impurity regions, said first contact being connected to said power supply line; a second contact region disposed opposite to said first contact region in at least one of said substrate and said impurity regions, said second contact region being connected to said CMOS structure; wherein said portion of said substrate which is formed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said memory cells.

Claim 20

A semiconductor memory device comprising: a semiconductor substrate and an impurity region, said substrate and region being of opposite conductivities; a plurality of memory cells which are comprised of a CMOS structure and formed in said substrate; and a power supply line for supplying a voltage to said memory cells, said power supply line being formed at a position away from said memory cells and electrically connected to said memory cells through a portion of said substrate which is located below said memory cells; a first contact region disposed in at least one of said substrates and said impurity regions, said first contact being connected to said power supply line; a second contact region disposed opposite to said first contact region in at least one of said substrate and said impurity regions, said second contact region being connected to said CMOS structure; wherein said portion of said substrate which is formed between said first and second contact regions functions as a resistor for thereby preventing an occurrence of a latch-up phenomenon of said memory cells.

Claim 21

A semiconductor memory device as recited in claim 15, wherein said resistor is disposed below said memory cells.