Reliable synchronous inter-node communication in a self-routing network

Claim 2

A packet switching network for communicating packets from network input ports to network output ports and each of said packets comprising routing information, said network comprising: a plurality of stages each comprising a plurality of switch nodes; said plurality of stages interconnected by a plurality of interstage links; each of said switch nodes comprising a plurality of input means and output means; each of said switch nodes further comprises a plurality of intra-node links; each input means of each of said switch nodes interconnected by a set of said intra-node links to all of the output means of the same switch node; each output means of each switch node of an upstream stage interconnected via one of said plurality of interstage links to an individual input means of a switch node of a downstream stage; one of said input means of a switch node of a downstream stage comprising means for generating packet clock signals for transmission to the output means of a switch node of the upstream stage via the interstage link upon said one of said input means having present capacity to receive a packet; one of said output means of said switch node of said upstream stage responsive to receipt of said packet clock signals for transferring one of said packets to said one of said input means of said switch node of said downstream stage; and said one of said output means of said switch node of said upstream stage comprises means responsive to the receipt of said packet clock signals from said one of said input means of said switch node of said downstream stage within a predefined amount of time following the end of transmission of said one of said packets for transmitting error information.

Claim 3

The network of claim 1 wherein one of said input means comprises means responsive to the end of transmission of said one of said packets for timing for said predefined amount of time before retransmitting said packet clock signals thereby indicating the reception of said one of said packets.

Claim 4

The network of claim 1 wherein said one of said input means of said switch node of said downstream stage further comprises means responsive to a system reset signal for generating said packet clock signals; and said one of said output means of said switch node of said upstream stage further comprises means in response to said system reset signal for generating said error information upon receipt of said packet clock signals not being received and the elapse of said predefined amount of time.

Claim 5

The network of claim 2 wherein said one of said output means of said switch node of said upstream stage comprises means responsive to packet clock signals and system clock signals for synchronizing the transfer of said one of said packets from said one of said output means of said switch node of said upstream stage to said one of said input means of said switch node of said downstream stage via said interconnecting link.

Claim 6

The network of claim 4 wherein said synchronizing means comprises means for individually storing data of said one of said packets; means responsive to said system clock signals for sequentially directing said data of said one of said packets into individual ones of said storing means; means responsive to said packet clock signals for sequentially reading the stored data of said one of said packets from said individual ones of said storing means in a different sequence than that used by said directing means in storing into said individual ones of said storing means; and means responsive to the read data of said one of said packets for transferring the latter data to said one of said input means of said switch node of said downstream stage via said interconnecting interstage link.

Claim 7

The network of claim 5 wherein said directing means comprises means responsive to said system clock signals for counting by modulo 3; and means responsive to the contents of said counting means for sequentially multiplexing said data of said one of said packets into individual ones of said storing means.

Claim 8

The system of claim 6 wherein said packet data comprises bits and said individual ones of said storing means are flip-flops comprising means for storing one bit of data of said one of said packets upon receipt of a flip-flop clock signal at a clock input terminal.

Claim 9

The network of claim 7 wherein said directing means further comprises another means for multiplexing said system clock signals to individual ones of said flip-flop clock input terminals as said flip-flop clock signals thereby causing said individual flip-flops to store said bits of said packet data of said one of said packets.

Claim 10

The network of claim 8 wherein said reading means comprises another means for counting by modulo 3 in response to said packet clock signals; and means for data selecting the contents of said flip-flops in response to the contents of said other counting means in a different sequence than that used by said directing means in storing said bits of said packet data of said one of said packets into said flip-flops.

Claim 11

A switch node for utilization in a packet switching network having a plurality of stages with each of said stages interconnected to an upstream stage by a first plurality of interstage links and to a downstream stage by a second plurality of interstage links and each stage comprising a plurality of said switch nodes for the communication of packets and, each of said plurality of said switch nodes interconnected to said upstream stage by a set of said first plurality of interstage links and to said downstream stage by a set of said second plurality of interstage links, and said switch node comprising: a plurality of input means for receiving packets from an upstream stage of said network via the set of said first plurality of interstage links; a plurality of output means for communicating packets from said switch node to a downstream stage via the set of said second plurality of interstage links; a plurality of intra-node links; each input means interconnected by a set of said intra-node links to all of said output means; one of said input means comprises means responsive to the present capacity of said one of said input means to receive a packet for generating a present capacity signal; means responsive to the generation of said present capacity signal for transmitting packet clocking signals from said one of said input means to said upstream stage on one link of said set of said first plurality of interstage links; means responsive to one of said packets from said upstream stage for storing said one of said packets; means further responsive to the storing of said one of said packets for requesting via one of said intranode links the transfer of said one of said packets by said one of said output means to said downstream stage via one link of said set of said second plurality of interstage links; and said one of said output means controlled by the transfer request and receipt of the packet clock signals from said downstream stage via said one link of said set of said second plurality of interstage links to communicate said one of said packets to said downstream stage via said one link of said set of said second plurality of interstage links.

Claim 12

A switch node for utilization in a packet switching network having a plurality of stages with each of said stages interconnected to an upstream stage by a first plurality of interstage links and to a downstream stage by a second plurality of interstage links and each stage comprising a plurality of said switch nodes for the communication of packets and, each of said plurality of said switch nodes interconnected to said upstream stage by a set of said first plurality of interstage links and to said downstream stage by a set of said second plurality of interstage links, and said switch node comprising: a plurality of input means for receiving packets from an upstream stage of said network via the set of said first plurality of interstage links; a plurality of output means for communicating packets from said switch node to a downstream stage via the set of said second plurality of interstage links; a plurality of intra-node links; each input means interconnected by a set of said intra-node links to all of said output means; one of said input means comprises means responsive to the present capacity of said one of said input means to receive a packet for generating a present capacity signal; means responsive to the generation of said present capacity signal for transmitting packet clocking signals from said one of said input means to said upstream stage on one link of said set of said first plurality of interstage links; means responsive to one of said packets from said upstream stage for storing said one of said packets; means further responsive to the storing of said one of said packets for requesting via one of said intranode links the transfer of said one of said packets by said one of said output means to said downstream stage via one link of said set of said second plurality of interstage links; and said one of said output means controlled by the transfer request and receipt of the packet clock signals from said downstream stage via said one link of said set of said second plurality of interstage links to communicate said one of said packets to said downstream stage via said one link of said set of said second plurality of interstage links.

Claim 13

The switch node of claim 10 wherein said one of said input means further comprises means responsive to the end of transmission of one of said packets from said upstream stage to cease transmitting said packet clock signals for a predefined amount of time thereby allowing said upstream stage to verify the correct operation of said one of said input means.

Claim 14

The switch node of claim 11 wherein said one of said output means further comprises means responsive to the end of transmission of said one of said packets to said downstream stage for generating an error signal upon receipt of said clock signals before said predefined amount of time elapsing.

Claim 15

The switch node of claim 10 wherein said one of said input means further comprises means responsive to a system reset signal for immediately transmitting said packet clock signals to said upstream stage.

Claim 16

The switch node of claim 13 wherein said one of said output means further comprises means responsive to said system reset signal for generating said error signal upon said packet clock signals not being received from said downstream stage within said predefined amount of time.

Claim 17

The output means of claim 12 further comprises means responsive to system clock signals and said packet clocking signals from said downstream stage for synchronizing the communication of said one of said packets from said one of said output means to said downstream stage.

Claim 18

The switch node of claim 13 wherein said rest means comprises first means responsive to said system clock signals for counting by modulo 3; means for individually storing data of said one of said packets; means responsive to said contents of said first counting means for sequentially directing said data of said one of said packets into individual ones of said storing means; second means for counting by modulo 3 in response to said packet clock signals; means responsive to contents of said second counting means for sequentially reading data of said one of said packets from individual ones of said storing means in a different sequence than that used by said directing means in storing into said individual ones of said storing means; and means responsive to the read data of said one of said packets for transferring said read data to said downstream stage.

Claim 19

The switch node of claim 16 wherein said individual ones of said storing means comprise flip-flops each having a data input and clock input terminals and responsive to a signal on said clock input terminal to store the bit present at said data input terminal; said data of said one of said packet comprises a plurality of data bits; said directing means comprises means for multiplexing said data bits to individual ones of said flip-flops in response to the contents of said first counting means; another means for multiplexing said system clock signals to the clock input terminal of individual ones of said flip-flops in response to said contents of said first counting means; and each of said individual flip-flops responsive to the receipt of one of said system clock signals for storing one of said data bits.

Claim 20

Error checking and control facilities for switch nodes of a packet switching network for the communication of packets and each of said nodes comprising a plurality of input means for receiving packets from an upstream one of said switch nodes and a plurality of output means for communicating packets from the switch node to a downstream switch node, said facilities comprising: means in a downstream switch node responsive to one of said input means having the present capacity for receiving a packet for transmitting packet clocking signals from said one of said input means to an upstream node; one of said output means in said upstream switch node comprising means for internally storing one of said packets; first means for counting by module 3 in response to system clock signals; a set of flip-flops to temporarily retain packet data of said one of said packets; means responsive to said system clock signals for storing said one of said packets from said internal storing means into said set of flip-flops under the direction of the contents of said module 3 counting means; second means for counting by module 3 in response to said packet clock signals from said one of said input means; means responsive to said second module 3 counting means for sequentially reading the packet data from said set of said flip-flops for transfer to said one of said input means of said downstream switch node; said one of said downstream switch nodes further comprises another internal storing means for storing the transferred packet data; means responsive to the end of transmission of said packet data for ceasing to transmit said packet clock signals to said upstream switch node; said upstream switch node further comprises means responsive to the end of transmission of said packet data for timing for a predefined period of time; and means responsive to said timing for generating an error signal upon said packet clocking signals being received during the entire length of said predefined time period.

Claim 21

Error checking and control facilities for switch nodes of a packet switching network for the communication of packets and each of said nodes comprising a plurality of input means for receiving packets from an upstream one of said switch nodes and a plurality of output means for communicating packets from the switch node to a downstream switch node, said facilities comprising: means in a downstream switch node responsive to one of said input means having the present capacity for receiving a packet for transmitting packet clocking signals from said one of said input means to an upstream node; one of said output means in said upstream switch node comprising means for internally storing one of said packets; first means for counting by module 3 in response to system clock signals; a set of flip-flops to temporarily retain packet data of said one of said packets; means responsive to said system clock signals for storing said one of said packets from said internal storing means into said set of flip-flops under the direction of the contents of said module 3 counting means; second means for counting by module 3 in response to said packet clock signals from said one of said input means; means responsive to said second module 3 counting means for sequentially reading the packet data from said set of said flip-flops for transfer to said one of said input means of said downstream switch node; said one of said downstream switch nodes further comprises another internal storing means for storing the transferred packet data; means responsive to the end of transmission of said packet data for ceasing to transmit said packet clock signals to said upstream switch node; said upstream switch node further comprises means responsive to the end of transmission of said packet data for timing for a predefined period of time; and means responsive to said timing for generating an error signal upon said packet clocking signals being received during the entire length of said predefined time period.

Claim 24

The method of claim 19 further comprises the step of retransmitting said packet clock signals by said one of said input means to said upstream switch node upon said predefined amount of time having elapsed.

Claim 25

The method of claim 20 further comprises the steps of: regenerating said packet clock signals by said one of said downstream input means upon receipt of a system reset signal; and retransmitting said error information by said upstream output means upon the elapse of said predefined amount of time and said system reset signal in absence of said packet clock signals.