Patent US4670846A successfully refreshed from Google Patents.
US4670846A
Expired / Lapsed
US
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Distributed bit integrated circuit design in a non-symmetrical data processing circuit
Assignee: Texas Instruments Inc
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Filing: 1984-05-01
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Granted: 1987-06-02
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Expires: 2004-05-01
Abstract
Abstract The present invention relates to construction of nonsymmetrical N bit parallel data processing circuits using a plurality of identical integrated circuits chips. In such nonsymmetrical structures it is often impossible to provide a design employing identical integrated circuit chips using conventional techniques. The structure is first divided into single bit slices. These single bit slices are then examined to determine the number of each differing single bit type. A common divisor M is sought for the entire set of B(I)'s, where B(I) is the number of bits of the I-th type. A partial structure is formed in which B(I)/M of each I-th bit type is provided. The number M identical integrated circuits of this partial structure are formed. Lastly, these identical integrated circuits are interconnected to form the whole structure desired. In the event such a common divisor M is not found, the B(J)'s are adjusted by subtraction from a subset bit type and addition to a superset bit type which includes all of the structures of the subset bit type. When the integrated circuits are interconnected the redundant circuits are not connected. This technique advantageously reduces the number of custom integrated circuits needed to construct a nonsymmetrical structure thus reducing design and tooling costs while increasing the volume of the identical integrated circuits thus reducing the costs of these integrated circuits.
Inventors
- 👤 Gerald E. Laws
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:33
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7896
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
142 words
A method for constructing a nonsymetrical N bit parallel data processing circuit comprising the steps of: identifying each different single bit type within the N bit parallel processing circuit, wherein a single bit type is a single bit having a unique, identifiable set of functions performable thereon by the N bit parallel data processing circuit; determining the number of bits B(I) which are of each I-th single bit type within the N bit parallel data processing circuit; determining a common divisor M of the number of bits B(I) for each single bit type, the common divisor M being greater than one; constructing M identical integrated circuits, each of said integrated circuits having B(I) divided by M number of bits of each I-th different single bit type; and interconnecting said M identical integrated circuits to form the N bit parallel data processing circuit.
Claim 2
Independent Claim
142 words
A method for constructing a nonsymetrical N bit parallel data processing circuit comprising the steps of: identifying each different single bit type within the N bit parallel processing circuit, wherein a single bit type is a single bit having a unique, identifiable set of functions performable thereon by the N bit parallel data processing circuit; determining the number of bits B(I) which are of each I-th single bit type within the N bit parallel data processing circuit; determining a common divisor M of the number of bits B(I) for each single bit type, the common divisor M being greater than one; constructing M identical integrated circuits, each of said integrated circuits having B(I) divided by M number of bits of each I-th different single bit type; and interconnecting said M identical integrated circuits to form the N bit parallel data processing circuit.
Claim 3
Dependent Claim
116 words
A method of constructing a non-symmetrical N bit parallel data processing circuit as claimed in claim 1, wherein: said N bit parallel data processing circuit includes an input bus having a plurality of parallel conductors connected to respective ones of the B(I) bits of the J-th single bit type; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a separate input pin for each of said B(J) divided by M bits of the J-th single bit type; and said step on interconnecting said M identical integrated circuits includes connecting said plurality of parallel conductors of said input bus to respective ones of said input pins of the J-th single bit type.
Claim 4
Dependent Claim
116 words
A method of constructing a non-symmetrical N bit parallel data processing circuit as claimed in claim 1, wherein: said N bit parallel data processing circuit includes an output bus having a plurality of parallel conductors connected to respective ones of the B(J) bits of the J-th single bit type; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a separate output pin for each of said B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting said plurality of parallel conductors of said output bus to respective ones of said output pins of the J-th single bit type.
Claim 5
Dependent Claim
113 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 1, wherein: said N bit parallel data processing circuit includes an input line connected to each of the B(J) bits of the J-th single bit type in parallel; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a single input pin connected to all of the B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting said input line to each of said single input pins of the J-th single bit type on each of said M integrated circuits.
Claim 6
Dependent Claim
118 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 1, wherein: said N bit parallel data processing circuit includes an output line connected to each of the B(J) bits of the J-th single bit type in parallel; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a single output pin connected to all of the B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting each of said single output pins of the J-th single bit type to an AND circuit, the output of said AND circuit being connected to said output line.
Claim 7
Independent Claim
189 words
A method of constructing a nonsymetrical N bit parallel data processing circuit comprising the steps of: identifying each different single bit type within the N bit parallel processing circuit, wherein a single bit type is a single bit having a unique, identifiable set of functions performable thereon by the N bit parallel data processing circuit; determining the number of bits B(I) which are of each I-th single bit type within the N bit parallel data processing circuit; creating P redundant circuits within an L-th single bit type by subtracting P from B(K) and adding P to B(L), the L-th single bit type being a superset of the K-th single bit type; determining a common divisor M of the number of bits B(I) for each single bit type, the common divisir M being greater than one; constructing M identical integrated circuits, each of said integrated circuits having B(I) divided by M number of bits of each I-th bit type; and interconnecting said M identical integrated circuits to form the N bits parallel data processing circuit, said interconnecting not including connecting said P redundant circuits of the L-th single bit type.
Claim 8
Independent Claim
189 words
A method of constructing a nonsymetrical N bit parallel data processing circuit comprising the steps of: identifying each different single bit type within the N bit parallel processing circuit, wherein a single bit type is a single bit having a unique, identifiable set of functions performable thereon by the N bit parallel data processing circuit; determining the number of bits B(I) which are of each I-th single bit type within the N bit parallel data processing circuit; creating P redundant circuits within an L-th single bit type by subtracting P from B(K) and adding P to B(L), the L-th single bit type being a superset of the K-th single bit type; determining a common divisor M of the number of bits B(I) for each single bit type, the common divisir M being greater than one; constructing M identical integrated circuits, each of said integrated circuits having B(I) divided by M number of bits of each I-th bit type; and interconnecting said M identical integrated circuits to form the N bits parallel data processing circuit, said interconnecting not including connecting said P redundant circuits of the L-th single bit type.
Claim 9
Dependent Claim
116 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an input bus having a plurality of parallel conductors connected to respective ones of the B(I) bits of the J-th single bit type; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a separate input pin for each of said B(J) divided by M bits of the J-th single bit type; and said step on interconnecting said M identical integrated circuits includes connecting said plurality of parallel conductors of said input bus to respective ones of said input pins of the J-th single bit type.
Claim 10
Dependent Claim
132 words
A method of constructing a nonsymmetrical N bit paralled data processing circuit as claimed in claim 6, wherein: said N bit paralled data processing circuit includes an input bus having a plurality of parallel conductors connected to respective ones of B(L) minus P of the L-th single bit type; said step of constructing said M identical integrated circuits includes constructing each integrated circuit having a separate input pin for each of said B(L) bits of the L-th single bit type; said step of interconnecting said M identical integrated circuits includes connecting said plurality of conductors of said input bus to respective ones of said input pins of B(L) minus P bits of said L-th single bit type and not connecting said input pins of P bits of said L-th single bit type.
Claim 11
Dependent Claim
116 words
A method of constructing a non-symmetrical N bit parallel data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an output bus having a pluralitv of parallel conductors connected to respective ones of the B(J) bits of the J-th single bit type; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a separate output pin for each of said B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting said plurality of parallel conductors of said output bus to respective ones of said output pins of the J-th single bit type.
Claim 12
Dependent Claim
134 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an output bus having a p1urality of parallel conductors connected to respective ones of B(L) minus P bits of said L-th single bit type; said step of constructing said M identical integrated circuits includes constructing each integrated circuit having a separate output pin for each of said B(L) bits of said L-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting said plurality of conductors of said output bus to respective ones of said output pins of B(L) minus P bits of said L-th single bit type and not connecting said output pins of P bits of said L-th single bit type.
Claim 13
Dependent Claim
113 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an input line connected to each of the B(J) bits of the J-th single bit type in parallel; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a single input pin connected to all of the B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting said input line to each of said single input pins of the J-th single bit type on each of said M integrated circuits.
Claim 14
Dependent Claim
141 words
A method of constructing a nonsymmetrical N bit paralled data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an input line connected to each of B(L) minus P bits of the L-th single bit type; said step of constructing M identical integrated circuits includes constructing each integrated circuit having first input pins for each of Q bits of the L-th type and having a single second input pin for all remaining bits of the L-th single bit type, where Q is P divided by M rounded up to the nearest integer; and said step of interconnecting said M identical integrated circuits includes connecting said input line to the input pins of said second input pins and Q minus P of said first input pins and not connecting P of said first input pins.
Claim 15
Dependent Claim
118 words
A method of constructing a nonsymmetrical N bit parallel data processing circuit as claimed in claim 6, wherein: said N bit parallel data processing circuit includes an output line connected to each of the B(J) bits of the J-th single bit type in parallel; said step of constructing M identical integrated circuits includes constructing each integrated circuit having a single output pin connected to all of the B(J) divided by M bits of the J-th single bit type; and said step of interconnecting said M identical integrated circuits includes connecting each of said single output pins of the J-th single bit type to an AND circuit, the output of said AND circuit being connected to said output line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |