US4670670A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for controlling threshold voltages in CMOS circuits
Assignee: Nokia Bell Labs
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Filing: 1984-10-05
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Granted: 1987-06-02
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Expires: 2004-10-05
Abstract
Abstract The threshold voltage of a CMOS circuit is stabilized by a feedback loop which responds to variations in threshold voltage of a reference FET to provide a backbias voltage to readjust the threshold voltage of a second FET. The circuit is particularly useful to overcome threshold variations due to γ-radiation.
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:50
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
190 words
A system comprising at least one CMOS integrated circuit chip, said chip including at least a first FET having a threshold voltage, said system further including a reference voltage terminal and feedback means for applying a backbias voltage to said first FET to correct for variations in said threshold voltage, said feedback means including an auxiliary FET with its gate terminal being coupled to its drain terminal, and with its drain terminal being coupled through a first resistor to the voltage reference terminal, said auxiliary FET and said first FET being integrated in said chip, said feedback means further including second and third resistors connected in series between the reference voltage terminal and a source terminal of the auxiliary FET, and said feedback means still further including an operational amplifier having a noninverting input terminal that is coupled to the drain terminal of the auxiliary FET and having an inverting terminal that is coupled to a node located between the second and third resistors, and said amplifier also having an output terminal coupled to the auxiliary FET and to the first FET in order to apply said backbias voltage thereto.
Claim 2
Independent Claim
190 words
A system comprising at least one CMOS integrated circuit chip, said chip including at least a first FET having a threshold voltage, said system further including a reference voltage terminal and feedback means for applying a backbias voltage to said first FET to correct for variations in said threshold voltage, said feedback means including an auxiliary FET with its gate terminal being coupled to its drain terminal, and with its drain terminal being coupled through a first resistor to the voltage reference terminal, said auxiliary FET and said first FET being integrated in said chip, said feedback means further including second and third resistors connected in series between the reference voltage terminal and a source terminal of the auxiliary FET, and said feedback means still further including an operational amplifier having a noninverting input terminal that is coupled to the drain terminal of the auxiliary FET and having an inverting terminal that is coupled to a node located between the second and third resistors, and said amplifier also having an output terminal coupled to the auxiliary FET and to the first FET in order to apply said backbias voltage thereto.
Claim 3
Dependent Claim
29 words
The system of claim 1 in which the second and third resistors are arranged such that the ratio of their resistances is a constant even when exposed to γ-radiation.
Claim 4
Dependent Claim
68 words
The system of claim 2 in which said operational amplifier has an offset voltage and in which said operatinal amplifier includes first and second input transistors each of which comprises two mutually similar separate parts connected together in parallel, each of said two separate parts of each of said input transistors being formed in a separate diffusion tub, in order to avoid a change in said offset voltage.
Claim 5
Dependent Claim
68 words
The system of claim 1 in which said operational amplifier has an offset voltage and in which said operational amplifier includes first and second input transistors each of which comprises two mutually similar separate parts connected together in parallel, each of said two separate parts of each of said input transistors being formed in a separate diffusion tub, in order to avoid a change in said offset voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |