Patent US4669098A successfully refreshed from Google Patents.
US4669098A
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Increased resolution counting circuit
Assignee: St Clair Intellectual Property Consultants Inc
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Filing: 1986-05-16
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Granted: 1987-05-26
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Expires: 2006-05-16
Abstract
Abstract A counting circuit includes a digital counter for counting the pulses of an input signal during a counting interval and a pair of digital latches for latching the binary state of the input signal at the beginning and end of the counting interval, respectively. The latched binary states of the input signal and the pulse count of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor. The interpreter resolves the pulse count into half clock cycles by comparing the binary states and in response adjusts the pulse count by the addition or subtraction of half a clock cycle.
Inventors
- 👤 John P. Boatwright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:22
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/40
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
126 words
A counting circuit for counting a binary input signal, comprising: counter means for counting the input signal pulses during a counting interval and generating in response a pulse count; first means for latching the binary state of the input signal present at the beginning of the counting interval; second means for latching the binary state of the input signal at the end of the counting interval; and interpreter means in communication with the counter means and the first and second latching means for interpreting the binary state of the input signal at the beginning and end of the counting interval upon completion of the interval and adjusting the value of the pulse count to resolve the input signal beyond the pulse count of the counter means.
Claim 2
Dependent Claim
126 words
A counting circuit for counting a binary input signal, comprising: counter means for counting the input signal pulses during a counting interval and generating in response a pulse count; first means for latching the binary state of the input signal present at the beginning of the counting interval; second means for latching the binary state of the input signal at the end of the counting interval; and interpreter means in communication with the counter means and the first and second latching means for interpreting the binary state of the input signal at the beginning and end of the counting interval upon completion of the interval and adjusting the value of the pulse count to resolve the input signal beyond the pulse count of the counter means.
Claim 3
Dependent Claim
69 words
The circuit of claim 1 in which the first and second latching means each comprise a digital latch receiving the input signal as an input, one of the latches enabled to latch the binary state of the input signal at the beginning of the counting interval and the other of the latches enabled to latch the binary state of the input signal at the end of the counting interval.
Claim 4
Dependent Claim
13 words
The circuit of claim 2 in which the digital latch is edge sensitive.
Claim 5
Dependent Claim
13 words
The circuit of claim 2 in which the digital latch is level sensitive.
Claim 6
Dependent Claim
48 words
The circuit of claim 1 in which the counter means comprises a digital counter that receives a clock signal as the binary input signal and receives a gating signal to control the counting interval, the counter generating a count of the clock pulses received during the counting interval.
Claim 7
Dependent Claim
49 words
The circuit of claim 5 in which the first and second means each comprise a digital latch receiving the clock signal as input, one of the latches enabled by a first transition of the gating signal and the other latch enabled by a second transition of the gating signal.
Claim 8
Dependent Claim
13 words
The circuit of claim 6 in which the digital counter is edge sensitive.
Claim 9
Dependent Claim
13 words
The circuit of claim 6 in which the digital counter is level sensitive.
Claim 10
Dependent Claim
39 words
The circuit of claim 1 in which the interpreter means comprises digital logic circuitry for evaluating the binary states of the input signal at the beginning and end of the counting interval and adjusting the pulse count in response.
Claim 11
Dependent Claim
38 words
The circuit of claim 1 in which the interpreter means comprises a microprocessor for evaluating the binary states of the input signal and the beginning and end of the counting interval and adjusting the pulse count in response.
Claim 12
Dependent Claim
112 words
A circuit for resolving the pulse count of a binary input signal to a digital counter, comprising: first means for latching the binary state of the input signal to the counter at the beginning of a counting interval; second means for latching the binary state of the input signal to the counter at the end of the counting interval; and interpreter means in communication with the digital counter and the first and second latching means for interpreting the binary states of the input signal at the beginning and end of the counting interval and in response adjusting the pulse count to resolve the input signal beyond the pulse count of the counter.
Claim 13
Dependent Claim
112 words
A circuit for resolving the pulse count of a binary input signal to a digital counter, comprising: first means for latching the binary state of the input signal to the counter at the beginning of a counting interval; second means for latching the binary state of the input signal to the counter at the end of the counting interval; and interpreter means in communication with the digital counter and the first and second latching means for interpreting the binary states of the input signal at the beginning and end of the counting interval and in response adjusting the pulse count to resolve the input signal beyond the pulse count of the counter.
Claim 14
Independent Claim
83 words
A method of counting pulses of a binary input signal, comprising: counting the input signal pulses during a counting interval, each signal pulse counted on the occurrence of a predetermined transition condition; detecting the binary state of the input signal at the beginning of the counting interval; detecting the binary state of the input signal at the end of the counting interval; and adjusting the pulse count in response to the detected binary states to resolve the input signal beyond the pulse count.
Claim 15
Independent Claim
83 words
A method of counting pulses of a binary input signal, comprising: counting the input signal pulses during a counting interval, each signal pulse counted on the occurrence of a predetermined transition condition; detecting the binary state of the input signal at the beginning of the counting interval; detecting the binary state of the input signal at the end of the counting interval; and adjusting the pulse count in response to the detected binary states to resolve the input signal beyond the pulse count.
References Cited (Backward Citations)
US4554674A
Cited
US4600845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-25 | 1990-11-24 | 1991-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-25 | 1994-11-24 | 1995-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-25 | 1998-11-24 | 1999-05-26 | $7700.00 | Window Closed / Lapsed |