Data processing system with a plurality of processors accessing a common bus to interleaved storage

Claim 1

A data processing system comprising: a first and a second storage unit responding to odd numbered and even numbered addresses respectively, each storage unit requiring more than a single information transfer interval to complete a storage transaction and said storage units including means for providing interleaved storage transactions; a common bus connected to said first and second storage units, said bus including arbitration means for regulating access to the bus and bus control means for providing pipelined operation of said bus; a plurality of processors connected to said common bus, and each including means for requesting access to the bus through the arbitration means and means for conducting transactions on said bus in accordance with said bus control means; and timing means for establishing a series of information transfer intervals; at least one of said processor having means for selectively commencing in response to bus access granted by the arbitration means, a storage transaction including an address transfer including a first address on said bus to one of said storage units during a transfer interval, the storage transaction initiated by said address transfer requiring more than one interval to complete, means for monitoring said bus in order to determine whether said first address on said bus has been transferred to said first or said second storage unit during said transfer interval, and said address transfer means further including means responsive to a determination that said first address has been transferred to said first or seond storage unit from said monitoring means for selectively transferring, in response to bus access granted by the arbitration means, the next subsequent address to the other of said storage units to establish interleaved storage transactions with said storage units.