Patent US4669000A successfully refreshed from Google Patents.
US4669000A
Expired / Lapsed
US
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Synchronizing circuit
Assignee: Sony Corp
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Filing: 1984-06-13
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Granted: 1987-05-26
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Expires: 2004-06-13
Abstract
Abstract This invention relate to a synchronizing circuit for a data signal in which a data signal is divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an arbitrary address signal and an error detection signal for the address signal and received so as to be written in a memory in accordance with the address signal, which includes means (4) for detecting the synchronizing signal and means (3) for detecting an error of the address signal. The circuit further comprising an interpolation synchronizing signal generating circuit (6) and an interpolation address signal generating circuit (10), in which when the address signal is judged as being correct by the error detecting means (3), the interpolation synchronizing signal generating circuit (6) is driven, the interpolation address signal generating circuit (10) is driven by an interpolation synchronizing signal from the interpolation synchronizing signal generating circuit (6), and the address signal and the interpolation address signal are changed over on the basis of whether the address signal is correct or erroneous and then fed to the memory (13 ). According to this invention, it is possible to establish the synchronization by a circuit of a simple construction.
Inventors
- 👤 Kentaro Odaka
- 👤 Tadashi Fukami
- 👤 Shinya Ozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:53
CPC Classifications
H; H03; H03K; H03K7/00; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; G11B20/00007; G11B20/10527; G11B20/12; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
207 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal so as to be transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal; means for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous by said means for detecting an error of said address signal, and means for gating said synchronizing signal with said detecting signal indicating said first state when said address signal is judged as being correct, and further comprising: memory means for storing said reproduced and transmitted data from said input terminal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means on the basis of whether said detecting signal indicates said first state or second state.
Claim 2
Dependent Claim
207 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal so as to be transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal; means for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous by said means for detecting an error of said address signal, and means for gating said synchronizing signal with said detecting signal indicating said first state when said address signal is judged as being correct, and further comprising: memory means for storing said reproduced and transmitted data from said input terminal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means on the basis of whether said detecting signal indicates said first state or second state.
Claim 3
Dependent Claim
61 words
A synchronizing circuit according to claim 1 further comprising: means for generating a second synchronizing signal; wherein said means for gating said synchronizing signal is provided with said synchronizing signal and said second synchronizing signal, and said means for gating said synchronizing signal is controlled by the output of said means for detecting an error or errors of said address signal.
Claim 4
Dependent Claim
25 words
A synchronizing circuit according to claim 2 further comprising means for controlling said means for selectively providing said address signal and said interpolation address signal.
Claim 5
Dependent Claim
18 words
A synchronizing circuit according to claim 1 wherein said data signal is a pulse code modulated audio signal.
Claim 6
Dependent Claim
23 words
A synchronizing circuit according to claim 1 wherein said data is recorded and reproduced by a rotary head of a helical scan type.
Claim 7
Dependent Claim
20 words
A synchronizing circuit according to claim 1, wherein said data signal is time base compressed and recorded and reproduced intermittently.
Claim 8
Dependent Claim
224 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal all of which are transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; memory means for storing said reproduced and transmitted data from said input terminal; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal and for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous, respectively; means controlled by the detecting signal of said means for detecting an error or errors of said address signal and for generating an internal synchronizing signal; means for gating said synchronizing signal with said internal synchronizing signal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means; and means for controlling said means for selectively providing said address signal and said interpolation address signals, on the basis of whether said detecting signal indicates said first state or second state.
Claim 9
Dependent Claim
224 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal all of which are transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; memory means for storing said reproduced and transmitted data from said input terminal; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal and for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous, respectively; means controlled by the detecting signal of said means for detecting an error or errors of said address signal and for generating an internal synchronizing signal; means for gating said synchronizing signal with said internal synchronizing signal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means; and means for controlling said means for selectively providing said address signal and said interpolation address signals, on the basis of whether said detecting signal indicates said first state or second state.
Claim 10
Dependent Claim
233 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal all of which are transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; memory means for storing said reproduced and transmitted data from said input terminal; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal and for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous, respectively; means controlled by the detecting signal of said means for detecting an error or errors of said address signal and for generating an internal synchronizing signal; means for driving a means for detecting an error or errors of said address signal with said internal synchronizing signal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means; and means for controlling said means for selectively providing said address signal and said interpolation address signal, on the basis of whether said detecting signal indicates said first state or second state.
Claim 11
Dependent Claim
233 words
A synchronizing circuit for reproduced data signals which are divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an address signal and an error detection signal for said address signal all of which are transmitted via a transmitting medium, the circuit comprising: an input terminal for receiving said transmitted data; memory means for storing said reproduced and transmitted data from said input terminal; means for detecting said synchronizing signal from said transmitted data; means for detecting said address signal from said transmitted data; means for detecting an error or errors of said address signal by utilizing said error detection signal and for generating a detecting signal indicating first and second states when said address signal is judged as being correct or erroneous, respectively; means controlled by the detecting signal of said means for detecting an error or errors of said address signal and for generating an internal synchronizing signal; means for driving a means for detecting an error or errors of said address signal with said internal synchronizing signal; means for generating an interpolation address signal; means for selectively providing said address signal and said interpolation address signal to said memory means; and means for controlling said means for selectively providing said address signal and said interpolation address signal, on the basis of whether said detecting signal indicates said first state or second state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-25 | 1990-11-24 | 1991-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-25 | 1994-11-24 | 1995-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-25 | 1998-11-24 | 1999-05-26 | $7700.00 | Window Closed / Lapsed |