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US4668969A
Expired / Lapsed
US
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Vertical non-single crystal semiconductor field effect transistor
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1984-07-23
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Granted: 1987-05-26
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Expires: 2004-07-23
Abstract
Abstract Apparatus is provided with at least a FET. The FET is formed of a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a insulating layer extending on the side surface of the second semiconductor layer and a conductive layer extending on the insulating layer in opposing relation to the side surface of the second semiconductor layer. In this case, the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer. The first and third semiconductor layers have the same conductivity type. The second semiconductor layer has a higher resistivity than the first and third semiconductor layers. The first and third semiconductor layers serve as either one of the drain and source and the other of them, respectively. The second semiconductor layer serves as channel region. The insulating layer and the conductive layer serve as gate insulating layer and gate electrode, respectively.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:52
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6728; H10D30/674; H10D30/6741; H10D30/675; H10D86/00; G02F1/136227; G02F1/13685
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
257 words
Apparatus with an FET, comprising: a first semiconductor layer formed on a substrate; a second semiconductor layer formed in as island-like pattern on the first semiconductor layer and having an area smaller than that of the latter; a third semiconductor layer formed on the second semiconductor layer in exactly the same size and pattern as the latter; a first insulating layer extending from the top surface of the third semiconductor layer to the top surface of the first semiconductor layer covering on the side surfaces of the second and third semiconductor layers; a first conductive layer formed on the first insulating layer in opposing relation to the top surface of third semiconductor layer, the side surfaces of the second and third semiconductor layers and the top surface of the first semiconductor layer; and a second conductive layer connected to the first conductive layer at a region overlying the first semiconductor layer; wherein the first, second and third semiconductor layers are formed of a non-single-crystal semiconductor doped with a dangling bond neutralizer; the first and third semiconductor layers have the same conductivity type; and the second semiconductor layer has a higher resistivity than the first and third semiconductor layers; and wherein the FET is constituted using the first and third semiconductor layers as either one of the drain and source and the other of them, the second semiconductor layer as channel region, the first conductive layer as a gate electrode, the first insulating layer as a gate insulating layer and the second conductive laYer as a gate lead.
Claim 2
Dependent Claim
257 words
Apparatus with an FET, comprising: a first semiconductor layer formed on a substrate; a second semiconductor layer formed in as island-like pattern on the first semiconductor layer and having an area smaller than that of the latter; a third semiconductor layer formed on the second semiconductor layer in exactly the same size and pattern as the latter; a first insulating layer extending from the top surface of the third semiconductor layer to the top surface of the first semiconductor layer covering on the side surfaces of the second and third semiconductor layers; a first conductive layer formed on the first insulating layer in opposing relation to the top surface of third semiconductor layer, the side surfaces of the second and third semiconductor layers and the top surface of the first semiconductor layer; and a second conductive layer connected to the first conductive layer at a region overlying the first semiconductor layer; wherein the first, second and third semiconductor layers are formed of a non-single-crystal semiconductor doped with a dangling bond neutralizer; the first and third semiconductor layers have the same conductivity type; and the second semiconductor layer has a higher resistivity than the first and third semiconductor layers; and wherein the FET is constituted using the first and third semiconductor layers as either one of the drain and source and the other of them, the second semiconductor layer as channel region, the first conductive layer as a gate electrode, the first insulating layer as a gate insulating layer and the second conductive laYer as a gate lead.
Claim 3
Dependent Claim
278 words
Apparatus with an FET, comprising: a second conductive layer formed on a substrate; a first semiconductor layer formed in as island-like pattern on the second conductive layer and having an area smaller than that of the latter; a second semiconductor layer formed on the first semiconductor layer including the same size and pattern as the latter; a third semiconductor layer formed on the second semiconductor layer in exactly the same size and pattern as the latter; a first insulating layer extending from the top surface of the third semiconductor layer to the top surface of the second conductive layer covering on the side surfaces of the first, second and third semiconductor layers; a first conductive layer formed on the first insulating layer in opposing relation to the top surface of third semiconductor layer, the side surfaces of the first, second and third semiconductor layers and the top surface of the second conductive layer; and a third conductive layer connected to the first conductive layer at a region overlying the second conductive layer; wherein the first, second and third semiconductor layers are formed of a non-single-crystal semiconductor doped with a dangling bond neutralizer; the first and third semiconductor layers have the same conductivity type; and the second semiconductor layer has a higher resistivity than the first and third semiconductor layers; and wherein the FET is constituted using the first and third semiconductor layers as either one of the drain and source and the other of them, the second semiconductor layer as channel region, the first conductive layer as a gate electrode, the first insulating layer as a gate insulating layer and the third conductive layer as a gate lead.
Claim 4
Dependent Claim
278 words
Apparatus with an FET, comprising: a second conductive layer formed on a substrate; a first semiconductor layer formed in as island-like pattern on the second conductive layer and having an area smaller than that of the latter; a second semiconductor layer formed on the first semiconductor layer including the same size and pattern as the latter; a third semiconductor layer formed on the second semiconductor layer in exactly the same size and pattern as the latter; a first insulating layer extending from the top surface of the third semiconductor layer to the top surface of the second conductive layer covering on the side surfaces of the first, second and third semiconductor layers; a first conductive layer formed on the first insulating layer in opposing relation to the top surface of third semiconductor layer, the side surfaces of the first, second and third semiconductor layers and the top surface of the second conductive layer; and a third conductive layer connected to the first conductive layer at a region overlying the second conductive layer; wherein the first, second and third semiconductor layers are formed of a non-single-crystal semiconductor doped with a dangling bond neutralizer; the first and third semiconductor layers have the same conductivity type; and the second semiconductor layer has a higher resistivity than the first and third semiconductor layers; and wherein the FET is constituted using the first and third semiconductor layers as either one of the drain and source and the other of them, the second semiconductor layer as channel region, the first conductive layer as a gate electrode, the first insulating layer as a gate insulating layer and the third conductive layer as a gate lead.
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