Semiconductor memory having load devices controlled by a write signal

Claim 1

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines each connected to a power source through respective load transistors; a plurality of memory cells connected to said word lines and said bit lines; a data input circuit for receiving data and transmitting the data to the memory cells for storage; a pair of data lines connected in common to the data input circuit, the bit lines, and a sense amplifier; and a switching circuit including means to turn off all of the respective load transistors when the data is being written in the memory cells, wherein the switching circuit has a first logic circuit for generating an output signal corresponding to the logical product of a chip select signal and an inverted write cycle signal, a second logic circuit receiving the output signal from the first logic circuit and generating an output signal corresponding to variations in the output signal from the first logic circuit, a first delay circuit for delaying the output signal from the second logic circuit by a predetermined time, a second delay circuit for further delaying the delayed signal from the first delay circuit by a time determined by the time required for storing data in the memory cells, and a flip-flop circuit receiving the outputs of the first and second delay circuits as a set and a reset input, respectively, and generating a signal which is fed to the load transistors to turn off the load transistors when data is being written in the memory cells.