Multiply and divide unit for a high speed processor

Claim 1

A multiply and divide unit for a high speed processor for performing a programmed mathematical operation on a first argument with a second argument to obtain a result thereby, the multiply and divide unit being responsive to a programmed instruction applied to the high speed processor and comprises: operation means for controlling a mathematical operation to be performed on the first and second arguments as instructed by the program instructions; first output register for registering a first part of the result of the mathematical operation; second output register for registering a second part of the result of the mathematical operation; A means for obtaining an A word from the first argument; first B means for obtaining a first B word and a first B compliment from the second argument and the first part; second B means for obtaining a second B word and a second B compliment word from the first B word; third B means for obtaining a third B word and a third B compliment word from a U word; fourth B means for obtaining obtaining a fourth B word and a fourth B word compliment from the first B word; recoder means for performing a Booth recode on the A word to obtain a Booth recoded A word; B selector means responsive to the Booth recoded A word for selecting a B word from the first B word, first B word compliment, second B word, second B word compliment, third B word, third B word compliment, forth B word, and fourth B word compliment; first selector means for selecting an A argument from the A word, the first B word, the second part, or a zero word; second selector means for selecting a B argument from the zero word, the B word, and the first part; adder means for adding the A argument and B argument to obtain a first summation word; more selector means for selecting the U word from the first summation word and the second part; least selector means for selecting a V word from the first summation word or the first part; modification means for modifying the V word to obtain a modified V word and includes a shift means for replacing a predetermined number of bits in the V word with a first logic state; first part selector means operatively connected to the first output register for selecting the first part from the U word and the modified V word; second part selector means operatively connected to the operations means for providing to the second part to the second output register selected from the U word, a modified U word, a first modified second part, and a second modified second part; and data bus for applying the zero word to the first and second selectors.