Patent US4664762A successfully refreshed from Google Patents.
US4664762A
Expired / Lapsed
US
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Method for etching a silicon substrate
Assignee: Denso Corp
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Filing: 1985-07-23
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Granted: 1987-05-12
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Expires: 2005-07-23
Abstract
Abstract A method of electrochemically etching a silicon substrate of a diaphragm type silicon pressure sensor is described. The etching process is accelerated by applying a positive voltage to, for example, an electrode of a P-type silicon layer of the substrate to be etched while the substrate is in an etchant solution.
Inventors
- 👤 Masaki Hirata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:42
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/61; H10P50/613; C; C25; C25F; C25F3/00; C25F3/02; C25F3/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
179 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; connecting an electrode to each of said first and second layers; applying a voltage between said electrodes including the steps of connecting the electrode on said P-type silicon layer to a positive terminal of a voltage source supplying said voltage, and connecting a negative terminal of said voltage source to said etchant; providing a switch selectively connecting said positive terminal of the voltage source and one of said electrodes, and setting the switch in a first position to connect to the P-type silicon layer to thereby increase the rate of etching; and when etching of the P-type silicon layer is approximately complete, moving the switch to a second position to connect the positive terminal of the voltage supply to the electrode of the N-type silicon layer whereby anodic-oxidization of said N-type silicon layer is accelerated concurrently with reduced rate of etching of said P-type silicon layer.
Claim 2
Independent Claim
179 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; connecting an electrode to each of said first and second layers; applying a voltage between said electrodes including the steps of connecting the electrode on said P-type silicon layer to a positive terminal of a voltage source supplying said voltage, and connecting a negative terminal of said voltage source to said etchant; providing a switch selectively connecting said positive terminal of the voltage source and one of said electrodes, and setting the switch in a first position to connect to the P-type silicon layer to thereby increase the rate of etching; and when etching of the P-type silicon layer is approximately complete, moving the switch to a second position to connect the positive terminal of the voltage supply to the electrode of the N-type silicon layer whereby anodic-oxidization of said N-type silicon layer is accelerated concurrently with reduced rate of etching of said P-type silicon layer.
Claim 3
Independent Claim
131 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; forming an electrode on each of said first and second layers; connecting a positive terminal of a voltage source to said electrode on said N-type silicon layer; connecting a negative terminal of said voltage source to said etchant; providing a switch selectively connecting said positive terminal to said electrode on said P-type silicon layer including the step of setting it at first to make said connection; and when etching of the P-type silicon layer is approximately complete, thus about to reach the N-type silicon layer, opening said switch to disconnect said P-type silicon layer from said positive terminal.
Claim 4
Independent Claim
131 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; forming an electrode on each of said first and second layers; connecting a positive terminal of a voltage source to said electrode on said N-type silicon layer; connecting a negative terminal of said voltage source to said etchant; providing a switch selectively connecting said positive terminal to said electrode on said P-type silicon layer including the step of setting it at first to make said connection; and when etching of the P-type silicon layer is approximately complete, thus about to reach the N-type silicon layer, opening said switch to disconnect said P-type silicon layer from said positive terminal.
Claim 5
Independent Claim
101 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; forming an electrode on each of said first and second layers; connecting a positive terminal of a first voltage source to said electrode on said N-type silicon layer; connecting a negative terminal of said first voltage source to said electrode on said P-type silicon layer and also to a positive terminal of a second voltage source; connecting a negative terminal of said second voltage source to said etchant.
Claim 6
Independent Claim
101 words
A method for etching one layer of a dual-layer silicon substrate having a first N-type silicon layer and a second P-type silicon layer, comprising the steps of: placing the substrate in an etchant; forming an electrode on each of said first and second layers; connecting a positive terminal of a first voltage source to said electrode on said N-type silicon layer; connecting a negative terminal of said first voltage source to said electrode on said P-type silicon layer and also to a positive terminal of a second voltage source; connecting a negative terminal of said second voltage source to said etchant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-11 | 1990-11-10 | 1991-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-11 | 1994-11-10 | 1995-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-11 | 1998-11-10 | 1999-05-12 | $7700.00 | Window Closed / Lapsed |