Computer control memory apparatus providing variable microinstruction length

Claim 1

Apparatus for providing a sequence of variable microinstructions having a first priority to a digital computer for controlling operations in said digital computer, wherein each variable microinstruction is made up of two microinstructions stored in and read from a memory in said computer, and execution of said sequence of variable microinstructions to control operations in the computer may be interrupted by an interruption signal generated within the computer in order that a higher priority sequence of microinstructions input to said computer from said memory may be executed before the computer completes execution of the first priority sequence of microinstructions, said apparatus comprising: a main control memory with addressable storage locations, each location containing a first microinstruction, said main control memory being provided with an input for addresses, and an output for first microinstructions read out of said main control memory in response to addresses on its input; a secondary control memory with addressable storage locations, each location containing a second microinstruction, said secondary control memory being provided with an input for addresses, and an output for second microinstructions read out of said secondary control memory in response to addresses on its input; means for jointly addressing said main and said secondary control memories to read said first and said second microinstructions therefrom, said addressing means being connected to said input of both said memories; a microinstruction register having a first and a second storage portion, said first storage portion being connected to said output of said main memory and receiving a first microinstruction therefrom; and said second storage portion receiving said second microinstruction read out of said secondary control memory, or a third microinstruction read out of an expansion register, or all zeroes, and the microinstructions or zeroes in said first and said second storage portions making up a variable microinstruction having a bit length equal to the sum of the bit lengths of the microinstructions or zeroes stored in said first and said second storage portions, said variable microinstruction for controlling operations in the computer, means for decoding connected to said microinstruction register for decoding said variable microinstruction received therein, said expansion register connected to said decoding means and said first storage portion and responsive to a decoded variable microinstruction to store a portion of said first storage portion, said expansion register also storing a microinstruction which is said third microinstruction; multiplexing means having a plurality of inputs to which are applied said second microinstructions stored in said secondary control memory, said third microinstructions stored in said expansion register, or all zeroes, and an output which is selectively connected to one of the plurality of inputs for outputting ones of the microinstructions or all zeroes from the inputs connected thereto to be stored in said second storage portion of said microinstruction register, a first one of said multiplexing means inputs being connected to said output of said secondary control memory, a second one of said multiplexing means inputs being connected to the output of said expansion register, and a third one of said multiplexing means inputs having a binary number of all zeroes input thereto, said multiplexing means output being connected to said second storage portion of said microinstruction register, and said multiplexing means having a first and a second control input to which are respectively applied first and second selection signals to control said multiplexing means; a first logical circuit having input thereto a portion of a microinstruction address from said addressing means and in response thereto generating said first selection signal which is applied to said first control input of said multiplexing means, said first selection signal being used to enable said multiplexing means to transfer a microinstruction or all zeroes from one of said three inputs of said multiplexer to said second storage portion of said microinstruction register; and second logical circuits connected to said decoding means and set by said interruption signal and reset by a decoded variable microinstruction of said first priority sequence of microinstructions, said second logical circuits being in their reset state generating said second selection signal which is applied to said second control input of said multiplexing means and enables said multiplexing means to connect one of the second or third microinstructions or all zeroes on said three inputs of said multiplexer to said second storage portion of said microinstruction register.