Low defect etching of patterns using plasma-stencil mask

Claim 3

The method according to claim 1 wherein each of said prescribed areas of said wafer surface contains a fiducial mark for use in aligning said wafer as one layer with other wafer layers in a multi-layer integrated circuit.

Claim 4

The method according to claim 1 wherein at least one wall of said vacuum chamber constitutes said second electrode.

Claim 5

The method according to claim 3 wherein the step of placing an apertured stencil includes spacing said stencil from said wafer surface by a distance which is, at most, twice the largest dimension of said stencil apertures.

Claim 6

The method according to claim 3 wherein the step of placing the semiconductor wafer includes disposing said wafer on a platen disposed in said chamber, and wherein the step of applying includes connecting said radio frequency potential between said platen and said second electrode.

Claim 7

The method according to claim 1 wherein the step of introducing includes delivering oxygen into said chamber.

Claim 8

The method according to claim 1 wherein the step of placing an apertured stencil includes spacing said stencil from said wafer surface by a distance which is, at most, twice the largest dimension of said stencil apertures.

Claim 9

The method according to claim 1 wherein the step of placing the semiconductor wafer includes disposing said wafer on a platen disposed in said chamber, and wherein the step of applying includes connecting said radio frequency potential between said platen and said second electrode.

Claim 10

The method according to claim 1 wherein the step of placing an apertured stencil includes spacing said stencil from said wafer surface by approximately fifty micrometers.

Claim 11

The method according to claim 9 wherein the step of placing the semiconductor wafer includes disposing said wafer on a platen disposed in said chamber, and wherein the step of applying includes connecting said radio frequency potential between said platen and said second electrode.

Claim 12

Apparatus for removing resist coating from the surface of a semiconductor wafer in the region of at least one fiducial mark on said surface, said fiducial mark being used for aligning said wafer with other wafers in a multi-wafer integrated circuit, said apparatus comprising: a chamber; pump means for exhausting gas from said chamber; supply means for delivering an etching gas into said chamber, said etching gas having at least one component which reacts chemically with said resist coating to form a volatile reaction plasma; platen means disposed in said chamber for supporting said wafer with said surface exposed and with said wafer in electrical contact with said platen means; a stencil having at least one aperture defined therethrough, said aperture having length and width dimensions sufficiently large to expose all of said fiducial mark; spacer means for supporting said stencil close to but spaced from said wafer surface with said aperture aligned with said fiducial mark, said spacer means being electrically conductive to tie said stencil to substantially the same potential as said wafer; and means for bombarding with energetic particles the plasma disposed between said stencil aperture and said wafer to enhance the etch rate of said resist coating by the bombarded plasma, said means for bombarding including means for directing said energetic particles in a direction substantially perpendicular to said stencil.

Claim 13

Apparatus for removing resist coating from the surface of a semiconductor wafer in the region of at least one fiducial mark on said surface, said fiducial mark being used for aligning said wafer with other wafers in a multi-wafer integrated circuit, said apparatus comprising: a chamber; pump means for exhausting gas from said chamber; supply means for delivering an etching gas into said chamber, said etching gas having at least one component which reacts chemically with said resist coating to form a volatile reaction plasma; platen means disposed in said chamber for supporting said wafer with said surface exposed and with said wafer in electrical contact with said platen means; a stencil having at least one aperture defined therethrough, said aperture having length and width dimensions sufficiently large to expose all of said fiducial mark; spacer means for supporting said stencil close to but spaced from said wafer surface with said aperture aligned with said fiducial mark, said spacer means being electrically conductive to tie said stencil to substantially the same potential as said wafer; and means for bombarding with energetic particles the plasma disposed between said stencil aperture and said wafer to enhance the etch rate of said resist coating by the bombarded plasma, said means for bombarding including means for directing said energetic particles in a direction substantially perpendicular to said stencil.

Claim 14

The apparatus according to claim 11 wherein said spacer means spaces said wafer surface from said stencil by a distance which is, at most, approximately twice the larger of said length and width dimensions of said aperture.

Claim 15

The apparatus according to claim 11 wherein said means for bombarding includes: a source of radio-frequency potential; first and second electrode means disposed in said chamber; and means connecting said radio-frequency potential between said first and second electrodes; wherein said platen means corresponds to said first electrode.

Claim 16

The apparatus according to claim 13 wherein said chamber has at least one electrically conductive wall spaced from said stencil by a spacing many times greater than the spacing between said wafer and said stencil, and wherein said wall corresponds to said second electrode.

Claim 17

The apparatus according to claim 14 wherein said chamber wall is electrically grounded.

Claim 18

The apparatus according to claim 15 wherein the spacing between said stencil and said wafer surface is approximately fifty micrometers.