US4660200A
Expired / Lapsed
US
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Method and apparatus for processing an error flag of a PCM signal
Assignee: Hitachi Ltd
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Filing: 1985-10-04
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Granted: 1987-04-21
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Expires: 2005-10-04
Abstract
Abstract Method and apparatus for reproducing a PCM signal are disclosed. The PCM signal comprises a plurality of word-interleaved frames. Each frame comprises a plurality of data blocks and a parity block. Each data block comprises a plurality of words, each word comprises an upper symbol and a lower symbol arranged symbol by symbol. A plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same word form a parity code generated from the symbols in the respective symbol sequences and a plurality of error detection/correction blocks. In the error flag processing of the PCM signal, the input PCM signal is reproduced, errors are detected and corrected based on the corresponding parity codes for a plurality of upper symbol error detection/correction sequences and a plurality of lower symbol error detection/correction sequences, error flags indicating the number of errors detected and the number of errors corrected are generated for the error detection/correction sequences based on the result of the error detection/correction, a flag indicating a maximum significant value is detected from two flags generated for the upper and lower symbol error detection/correction sequence of the same word and selecting that flag as a common flag to both sequences.
Inventors
- 👤 Hiroo Okamoto
- 👤 Masaharu Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:11
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/02; G11B20/08; G11B20/10; G11B20/18; G11B20/1876; G11B20/10527; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
A method for processing a PCM signal comprising a plurality of frames having interleaved words, each frame including a plurality of data blocks and parity blocks, each data block including a plurality of words, each word comprising an upper symbol and a lower symbol arranged symbol by symbol, a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same word forming parity codes generated by the symbols in the respective symbol sequences and a plurality of error detection/correction blocks; said method comprising the steps of: (a) reproducing the input PCM signal and detecting and correcting errors based on corresponding parity codes for the upper symbol error detection/correction sequences and lower symbol error detection/correction sequences; (b) generating an error flag indicating whether an incorrectable error or errors are present for each error detection/correction sequence based on the result of the error detection/correction; and (c) detecting a flag indicating a maximum significant value based on two flags generated for the error detection/correction sequences for the upper symbol and the lower symbol in one word and selecting the detected flag as a common flag to both sequences.
Claim 2
Independent Claim
192 words
A method for processing a PCM signal comprising a plurality of frames having interleaved words, each frame including a plurality of data blocks and parity blocks, each data block including a plurality of words, each word comprising an upper symbol and a lower symbol arranged symbol by symbol, a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same word forming parity codes generated by the symbols in the respective symbol sequences and a plurality of error detection/correction blocks; said method comprising the steps of: (a) reproducing the input PCM signal and detecting and correcting errors based on corresponding parity codes for the upper symbol error detection/correction sequences and lower symbol error detection/correction sequences; (b) generating an error flag indicating whether an incorrectable error or errors are present for each error detection/correction sequence based on the result of the error detection/correction; and (c) detecting a flag indicating a maximum significant value based on two flags generated for the error detection/correction sequences for the upper symbol and the lower symbol in one word and selecting the detected flag as a common flag to both sequences.
Claim 3
Dependent Claim
48 words
A method for processing a PCM signal according to claim 1 further comprising the steps of determining if an incorrectable error is included in the word based on the common flag added to the error detection/correction sequence and concealing the word based on the result of the determination.
Claim 4
Independent Claim
246 words
A method for reproducing a PCM signal having words each comprising an upper symbol and a lower symbol, each block comprising a plurality of upper symbols and a plurality of lower symbols, a second error detection/correction code being added to each of a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same PCM signals as those in which said plurality of upper symbols are included, a first error detection/correction code being added to each of a plurality of upper symbols and lower symbols of a plurality of PCM signals included in different second error detection/correction code sequences (plural-block interleaved symbols) or a plurality of second error detection/correction codes; said method comprising the steps of: (a) detecting and correcting errors for the first error detection/correction code as first error detection/correction step; (b) adding a first error flag indicating whether an incorrectable error or errors are present for each of the first error detection/correction sequences; (c) detecting and correcting errors for the second error detection/correction code as second error detection/correction step, generating a second flag indicating an incorrectable error if the error is incorrectable, and adding a flag indicating a maximum significant value of the code sequences to the second error detection/correction code including the upper symbol and the lower symbol of the PCM signal; and (d) determining if the PCM signal includes an incorrectable error or not based on said first error flag and said second error flag.
Claim 5
Independent Claim
246 words
A method for reproducing a PCM signal having words each comprising an upper symbol and a lower symbol, each block comprising a plurality of upper symbols and a plurality of lower symbols, a second error detection/correction code being added to each of a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same PCM signals as those in which said plurality of upper symbols are included, a first error detection/correction code being added to each of a plurality of upper symbols and lower symbols of a plurality of PCM signals included in different second error detection/correction code sequences (plural-block interleaved symbols) or a plurality of second error detection/correction codes; said method comprising the steps of: (a) detecting and correcting errors for the first error detection/correction code as first error detection/correction step; (b) adding a first error flag indicating whether an incorrectable error or errors are present for each of the first error detection/correction sequences; (c) detecting and correcting errors for the second error detection/correction code as second error detection/correction step, generating a second flag indicating an incorrectable error if the error is incorrectable, and adding a flag indicating a maximum significant value of the code sequences to the second error detection/correction code including the upper symbol and the lower symbol of the PCM signal; and (d) determining if the PCM signal includes an incorrectable error or not based on said first error flag and said second error flag.
Claim 6
Dependent Claim
262 words
A PCM signal reproduction apparatus for reproducing a PCM signal having words each comprising an upper symbol and a lower symbol, each block comprising a plurality of upper symbols and a plurality of lower symbols, a second error detection/correction code being added to each of a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same PCM signals as those in which said plurality of upper symbols are included, a first error detection/correction code being added to each of a plurality of upper symbols and lower symbols of a plurality of PCM signals included in different second error detection/correction code sequences (plural-block interleaved symbols) or a plurality of second error detection/correction codes; comprising: a demodulator for reproducing a digital signal from a reproduced signal; a readable/writable memory for storing the digital signal reproduced by said demodulator, a corrected PCM signal and error flags; an error correction circuit for effecting first and second error detections/corrections by error detection/correction code sequences for the reproduced digital signal stored in said memory and generating first and second error flags; an error flag processor for selecting, as a second error flag, a maximum significant value of the error flags added to the second error detection/correction code sequence comprising only the upper symbols and the second error detection/correction code sequence comprising only the lower symbols, and an error concealment circuit for determining if the PCM signal includes an incorrectable error or not based on said first and second error flags and concealing the error if the incorrectable error is included.
Claim 7
Dependent Claim
262 words
A PCM signal reproduction apparatus for reproducing a PCM signal having words each comprising an upper symbol and a lower symbol, each block comprising a plurality of upper symbols and a plurality of lower symbols, a second error detection/correction code being added to each of a plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same PCM signals as those in which said plurality of upper symbols are included, a first error detection/correction code being added to each of a plurality of upper symbols and lower symbols of a plurality of PCM signals included in different second error detection/correction code sequences (plural-block interleaved symbols) or a plurality of second error detection/correction codes; comprising: a demodulator for reproducing a digital signal from a reproduced signal; a readable/writable memory for storing the digital signal reproduced by said demodulator, a corrected PCM signal and error flags; an error correction circuit for effecting first and second error detections/corrections by error detection/correction code sequences for the reproduced digital signal stored in said memory and generating first and second error flags; an error flag processor for selecting, as a second error flag, a maximum significant value of the error flags added to the second error detection/correction code sequence comprising only the upper symbols and the second error detection/correction code sequence comprising only the lower symbols, and an error concealment circuit for determining if the PCM signal includes an incorrectable error or not based on said first and second error flags and concealing the error if the incorrectable error is included.
Claim 8
Dependent Claim
36 words
A PCM signal reproduction apparatus according to claim 4 wherein said first and second error flags are stored in an area of said memory at which said first and/or second error detection/correction codes have been stored.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-20 | 1998-10-20 | 1999-04-21 | $7700.00 | Window Closed / Lapsed |