Patent US4660181A successfully refreshed from Google Patents.
US4660181A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system
Assignee: Toshiba Corp
•
Filing: 1985-03-21
•
Granted: 1987-04-21
•
Expires: 2005-03-21
Abstract
Abstract A memory system includes a memory which consists of a plurality of bit memory cells each capable of being independently accessible and of storing bit data in at least a first and a second different predetermined bit width access mode. A multiplexer and address decoder are provided together with a bit width register for producing first and second write control signals corresponding to the first and second access modes respectively for enabling writing within the independently accessible memory cells of data having respectively first and a different second bit width.
Inventors
- 👤 Mitsuo Saito
- 👤 Takeshi Aikawa
- 👤 Akio Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:43
CPC Classifications
G; G11; G11C; G11C8/00; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G11C7/00; G11C7/10; G11C7/1006; G11C8/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
215 words
A memory system, comprising: a memory consisting of a plurality of bit memory cells, each capable of being independently accessible and of storing bit data in at least a first and second different predetermined bit width access modes; multiplexer means for receiving addresses corresponding to each access mode and for selectively producing at least first and second predetermined address bit portions out of each of the addresses for applying each of said first and second address bit portions to said memory in accordance respectively with said first and second predetermined bit width access modes; address decoder means connected between said multiplexer means and said memory for receiving another predetermined address bit portion for at least said first access mode and for decoding said other predetermined address bit portion for producing a first write control signal for designating at least one particular bit to be accessed; a bit width register for receiving a bit width designating signal in said second access mode and for producing a second write control signal when said second bit width access mode is to be performed; and said memory connected for receiving said first and second write control signals in said first and second access modes respectively for writing therein data having respectively a first and a different second bit width.
Claim 2
Dependent Claim
215 words
A memory system, comprising: a memory consisting of a plurality of bit memory cells, each capable of being independently accessible and of storing bit data in at least a first and second different predetermined bit width access modes; multiplexer means for receiving addresses corresponding to each access mode and for selectively producing at least first and second predetermined address bit portions out of each of the addresses for applying each of said first and second address bit portions to said memory in accordance respectively with said first and second predetermined bit width access modes; address decoder means connected between said multiplexer means and said memory for receiving another predetermined address bit portion for at least said first access mode and for decoding said other predetermined address bit portion for producing a first write control signal for designating at least one particular bit to be accessed; a bit width register for receiving a bit width designating signal in said second access mode and for producing a second write control signal when said second bit width access mode is to be performed; and said memory connected for receiving said first and second write control signals in said first and second access modes respectively for writing therein data having respectively a first and a different second bit width.
Claim 3
Dependent Claim
38 words
The memory system as claimed in claim 1, wherein said predetermined bit width access modes consists of at least a 16-bit width, a 1-bit width, a 2-bit width, a 4-bit width access, and an 8-bit width access mode.
Claim 4
Dependent Claim
37 words
The memory system as claimed in claim 1, wherein said second predetermined address bit portion is A 0 -A 11 which designates a particular word stored in said memory, when a 16-bit width access mode is performed.
Claim 5
Dependent Claim
37 words
The memory system as claimed in claim 1, wherein said first predetermined address bit portion is A 4 -A 15 which designates a particular word stored in said memory when a 1-bit width access mode is performed.
Claim 6
Dependent Claim
34 words
The memory system as claimed in claim 4, wherein said other predetermined address bit portion is A 0 -A 3 which designates at least one particular bit when the 1-bit width access is performed.
Claim 7
Dependent Claim
32 words
The memory system as claimed in claim 1, wherein said first bit width access mode is the 16-bit width access while said second bit width access mode is the 1-bit width access.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-20 | 1998-10-20 | 1999-04-21 | $7700.00 | Window Closed / Lapsed |