Dual electron injection structure and process with self-limiting oxidation barrier

Claim 1

A method for incorporating a non-continuous DEIS structure between multiple layers of polysilicon in an array of devices on an integrated circuit substrate comprising the following steps: (a) fabricating at least one thin oxide region surrounded by thick oxide regions on a silicon substrate; (b) depositing a first polysilicon gate interconnect layer on the substrate; (c) depositing a layer of silicon rich nitride on said polysilicon gate interconnect layer; (d) patterning a first photoresist mask on the silicon rich nitride layer with said photoresist mask defining a profile for the silicon rich nitride; (e) etching the uncovered areas of the silicon rich nitride; (f) patterning a second mask on the first polysilicon gate interconnect layer with said second mask defining a profile for the first polysilicon gate interconnect layer; (g) etching the uncovered areas of the first polysilicon gate interconnect layer; (h) etching back the thin oxide region in step (a) to the silicon substrate; (i) growing an oxide layer of sufficient thickness on the silicon rich nitride, the first polysilicon gate interconnect layer and oxidizing the silicon substrate of step (h); (j) depositing a layer of silicon rich oxide on the oxide layer of step (i); (k) depositing a second polysilicon layer on the silicon rich oxide of step (j); and (l) patterning the second polysilicon layer of step (k) to form at least one gate electrode.

Claim 2

A method for incorporating a non-continuous DEIS structure between multiple layers of polysilicon in an array of devices on an integrated circuit substrate comprising the following steps: (a) fabricating at least one thin oxide region surrounded by thick oxide regions on a silicon substrate; (b) depositing a first polysilicon gate interconnect layer on the substrate; (c) depositing a layer of silicon rich nitride on said polysilicon gate interconnect layer; (d) patterning a first photoresist mask on the silicon rich nitride layer with said photoresist mask defining a profile for the silicon rich nitride; (e) etching the uncovered areas of the silicon rich nitride; (f) patterning a second mask on the first polysilicon gate interconnect layer with said second mask defining a profile for the first polysilicon gate interconnect layer; (g) etching the uncovered areas of the first polysilicon gate interconnect layer; (h) etching back the thin oxide region in step (a) to the silicon substrate; (i) growing an oxide layer of sufficient thickness on the silicon rich nitride, the first polysilicon gate interconnect layer and oxidizing the silicon substrate of step (h); (j) depositing a layer of silicon rich oxide on the oxide layer of step (i); (k) depositing a second polysilicon layer on the silicon rich oxide of step (j); and (l) patterning the second polysilicon layer of step (k) to form at least one gate electrode.

Claim 7

A method for fabricating an improved semi-conductor module comprising the steps of: (a) providing a silicon substrate having at least one thin oxide region thereon; (b) depositing a first polysilicon gate interconnecting layer on the substrate; (c) depositing a silicon rich nitride (SRN) layer on the first polysilicon gate interconnecting layer; (d) depositing a silicon dioxide (SiO 2 ) layer on the SRN layer; (e) masking the SiO 2 layer; (f) etching the unmasked section of the SRN layer, the SiO 2 layer and the unmasked section of first polysilicon gate layer; (g) etching back the thin oxide region of step (a) to the silicon substrate; (h) stripping the mask in step (e); (i) thermally oxidizing the module; (j) depositing a layer of silicon rich oxide on the SiO 2 layer of step (d); (k) depositing a second polysilicon gate interconnecting layer on the silicon rich oxide layer in step (j); and (l) generating gate electrode and poly 2 devices in said interconnecting layer of step (k).

Claim 8

A method for fabricating an improved semi-conductor module comprising the steps of: (a) providing a silicon substrate having at least one thin oxide region thereon; (b) depositing a first polysilicon gate interconnecting layer on the substrate; (c) depositing a silicon rich nitride (SRN) layer on the first polysilicon gate interconnecting layer; (d) depositing a silicon dioxide (SiO 2 ) layer on the SRN layer; (e) masking the SiO 2 layer; (f) etching the unmasked section of the SRN layer, the SiO 2 layer and the unmasked section of first polysilicon gate layer; (g) etching back the thin oxide region of step (a) to the silicon substrate; (h) stripping the mask in step (e); (i) thermally oxidizing the module; (j) depositing a layer of silicon rich oxide on the SiO 2 layer of step (d); (k) depositing a second polysilicon gate interconnecting layer on the silicon rich oxide layer in step (j); and (l) generating gate electrode and poly 2 devices in said interconnecting layer of step (k).