Dual slope converter with large apparent integrator swing

Claim 2

In an integrating analog to digital converter of the type in which an integrator is charged to a level established by an unknown input signal during an integrate phase of fixed time and is then deintengrated during a deintegrate phase until the integrator output reaches a predetermined level, wherein the deintegration phase is measured by clock pulses occurring at predetermined intervals, the improvement wherein the duration of the fixed integration phase is less than one full power cycle period and the converter further comprises means for holding the integrator output constant at the end of the deintegrate phase to define a rest phase until the beginning of a subsequent integrate phase, and means for repeating the integrate and subsequent deintegrate and rest phases until the total duration of the integrate phases is equal to an integral multiple of the power line cycle, the integrate phases being timed to occur at various portions of the power line cycle to reject power line noise.

Claim 3

The converter of claim 1 wherein the total duration of the integrate phases is 1/60th of a second.

Claim 4

The converter of claim 1 wherein the power line period is 1/60th of a second.

Claim 5

The converter of claim 1 wherein the duration of each fixed integrate phase is equal to one full power line cycle divided by a factor equal to a power of two.

Claim 6

The converter of claim 4 wherein the total duration of each combined deintegrate phase and rest phase is equal to an integral multiple of the integrate phase.

Claim 7

The converter of claim 1 wherein the duration of the integrate phase is 1/240th of a second and the duration of each combined deintegrate phase and rest phase is 1/120th of a second.

Claim 10

An integrating analog to digital converter for converting an unknown analog signal to a digital value, comprising: an integrator for integrating the analog signal; detection means for detecting when the output of the integrator reaches a predetermined value; and control means responsive to the detection means for operating the integrator in multiple cycles in which each cycle comprises an integrate phase of a fixed duration which is less than one full power line cycle, and a deintegrate phase and a rest phase, the combined durations of which are equal to an integral multiple of the duration of the integrate phase, wherein the control means comprises means for; (1) causing the integrator to integrate the analog signal for the predetermined duration of the integrate phase, (2) causing the integrator to deintegrate the integrated signal during the deintegration phase until the integrated signal reaches a predetermined level, marking the termination of the deintegrate phase, (3) causing the output of the integrator to remain constant during the rest phase until the combined duration of the deintegrate phase and the rest phase are equal to said multiple of the integrate phase so that the subsequent integrating step occurs at a different portion of the power line cycle, and (4) repeating each cycle of an integrate phase, a deintegrate phase and a rest phase until the combined durations of the integrate phases correspond to each portion of an integral multiple of the power line cycle.

Claim 11

An integrating analog to digital converter for converting an unknown analog signal to a digital value, comprising: an integrator for integrating the analog signal; detection means for detecting when the output of the integrator reaches a predetermined value; and control means responsive to the detection means for operating the integrator in multiple cycles in which each cycle comprises an integrate phase of a fixed duration which is less than one full power line cycle, and a deintegrate phase and a rest phase, the combined durations of which are equal to an integral multiple of the duration of the integrate phase, wherein the control means comprises means for; (1) causing the integrator to integrate the analog signal for the predetermined duration of the integrate phase, (2) causing the integrator to deintegrate the integrated signal during the deintegration phase until the integrated signal reaches a predetermined level, marking the termination of the deintegrate phase, (3) causing the output of the integrator to remain constant during the rest phase until the combined duration of the deintegrate phase and the rest phase are equal to said multiple of the integrate phase so that the subsequent integrating step occurs at a different portion of the power line cycle, and (4) repeating each cycle of an integrate phase, a deintegrate phase and a rest phase until the combined durations of the integrate phases correspond to each portion of an integral multiple of the power line cycle.

Claim 12

The converter of claim 8 wherein the integral multiple of the power line cycle in a single power line cycle.

Claim 13

In an integrating analog to digital converter of the type in which an integrator is charged to a level established by an unknown input signal during an integrate phase of a predetermined number of clock pulses and is then deintegrated during a deintegrate phase until the integrator output reaches a predetermined level as determinined by a comparator, said integrator output overshooting the predetermined level to a residual level, wherein the deintegrate phase is measured by counting clock pulses, the improvement wherein the converter further comprises means for holding the integrator output at the residual level upon termination of the deintegrate phase and during a rest phase and until the initiation of a subsequent integrator phase at a different portion of the power line cycle, and means for repeating the integrate, deintegrate and rest phases until the total duration of the integrate phases is equal to second predetermined number of clock pulses; wherein the total number of clock pulses during the deintegrate phase is a digital representation of the unknown input signal.

Claim 14

In an integrating analog to digital converter of the type in which an integrator is charged to a level established by an unknown input signal during an integrate phase of a predetermined number of clock pulses and is then deintegrated during a deintegrate phase until the integrator output reaches a predetermined level as determinined by a comparator, said integrator output overshooting the predetermined level to a residual level, wherein the deintegrate phase is measured by counting clock pulses, the improvement wherein the converter further comprises means for holding the integrator output at the residual level upon termination of the deintegrate phase and during a rest phase and until the initiation of a subsequent integrator phase at a different portion of the power line cycle, and means for repeating the integrate, deintegrate and rest phases until the total duration of the integrate phases is equal to second predetermined number of clock pulses; wherein the total number of clock pulses during the deintegrate phase is a digital representation of the unknown input signal.

Claim 15

The converter of claim 10 wherein the total duration of the second predetermined number of clock pulses of the integrate phases is equal to an integral multiple of the power line cycle.

Claim 16

The converter of claim 10 wherein the total duration of the second predetermined number of clock pulses of the integration phases is 1/60th of a second.

Claim 17

The converter of claim 10 wherein the total duration of the first predetermined number of clock pulses of the integrate phase is equal to one full power line cycle divided by a factor equal to a power of two.

Claim 18

The converter of claim 13 wherein the total duration of each combined deintegrate phase and rest phase is equal to an integral multiple of the integrate phase.

Claim 19

The converter of claim 10 wherein the duration of each integrate phase is 1/240th of a second and the combined duration of each deintegrate phase and subsesquent rest phase is 1/120th of a second.