US4654823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read/write memory and cell constituting same
Assignee: ALE International SAS
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Filing: 1985-04-08
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Granted: 1987-03-31
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Expires: 2005-04-08
Abstract
Abstract A read/write memory cell comprises a first switch having one input which constitutes the data input-output of the cell and another input connected to a loop circuit comprises a first inverter, a second inverter and a second switch. The first and second switches are controlled in such a way that on a write operation the first is closed and the second open. In the absence of any write or read operation the first switch is open and the second switch is closed. On a read operation both switches are closed. A read/write memory of N words each of P bits is obtained by associating N×P cells of this kind in a matrix comprising N rows and P columns.
Inventors
- 👤 Pierre Charransol
- 👤 Jean-Claude Audrix
- 👤 Jacques Gouit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/4023
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
155 words
Read/write memory cell comprising a first switch, a loop circuit comprising a first inverter, a second inverter and a second switch, said first switch having a first transfer terminal connected to a data input-output of the cell and a second transfer terminal connected to an input of said first inverter, said first inverter having an output connected to and input of said second inverter, said second inverter having an output connected to a first transfer terminal of said second switch, said second switch having a second transfer terminal connected to said second transfer terminal of said first switch, and means for controlling said first and second switches whereby on a write operation said first switch is closed and said second switch is open, on a read operation said first and second switches are closed, and when no write or read operation is in progress, said first switch is open and said second switch is closed.
Claim 2
Dependent Claim
155 words
Read/write memory cell comprising a first switch, a loop circuit comprising a first inverter, a second inverter and a second switch, said first switch having a first transfer terminal connected to a data input-output of the cell and a second transfer terminal connected to an input of said first inverter, said first inverter having an output connected to and input of said second inverter, said second inverter having an output connected to a first transfer terminal of said second switch, said second switch having a second transfer terminal connected to said second transfer terminal of said first switch, and means for controlling said first and second switches whereby on a write operation said first switch is closed and said second switch is open, on a read operation said first and second switches are closed, and when no write or read operation is in progress, said first switch is open and said second switch is closed.
Claim 3
Dependent Claim
11 words
Cell according to claim 1, implemented as an MOS integrated circuit.
Claim 4
Dependent Claim
68 words
Cell according to claim 2, wherein each of said switches comprises a P-type MOS transistor and an N-type MOS transistor in parallel having their transfer electrodes connected in pairs and their respective control electrodes connected to receive from said control means two complementary signals A and A in the case of said first switch and two complementary signals B and B in the case of said second switch.
Claim 5
Dependent Claim
295 words
Memory with N words each of P bits comprising N×P read/write memory cells each comprising a first switch, a loop circuit comprising a first inverter, a second inverter and a second switch, said first switch having a first transfer terminal connected to a data input-output of the cell and a second transfer terminal connected to an input of said first inverter, said first inverter having an output connected to and input of said second inverter, said second inverter having an output connected to a first transfer terminal of said second switch, said second switch having a second transfer terminal connected to said second transfer terminal of said first switch, and means for controlling said first and second switches whereby on a write operation said first switch is closed and said second switch is open, on a read operation said first and second switches are closed, and when no write or read operation is in progress, said first switch is open and said second switch is closed, wherein each of said switches comprises a P-type MOS transistor and an N-type MOS transistor in parallel having their transfer electrodes connected in pairs and their respective control electrodes connected to receive two complementary signals A and A in the case of said first switch and two complementary signals B and B in the case of said second switch, in which memory said cells are arranged in a matrix comprising N rows and P columns, the MOS transistors constituting said first switch of the cells in the same row n are controlled by the same signals X n and X n and the MOS transistors constituting said second switch of the cells in the same column p are controlled by the same signals Y p and Y p .
Claim 6
Dependent Claim
295 words
Memory with N words each of P bits comprising N×P read/write memory cells each comprising a first switch, a loop circuit comprising a first inverter, a second inverter and a second switch, said first switch having a first transfer terminal connected to a data input-output of the cell and a second transfer terminal connected to an input of said first inverter, said first inverter having an output connected to and input of said second inverter, said second inverter having an output connected to a first transfer terminal of said second switch, said second switch having a second transfer terminal connected to said second transfer terminal of said first switch, and means for controlling said first and second switches whereby on a write operation said first switch is closed and said second switch is open, on a read operation said first and second switches are closed, and when no write or read operation is in progress, said first switch is open and said second switch is closed, wherein each of said switches comprises a P-type MOS transistor and an N-type MOS transistor in parallel having their transfer electrodes connected in pairs and their respective control electrodes connected to receive two complementary signals A and A in the case of said first switch and two complementary signals B and B in the case of said second switch, in which memory said cells are arranged in a matrix comprising N rows and P columns, the MOS transistors constituting said first switch of the cells in the same row n are controlled by the same signals X n and X n and the MOS transistors constituting said second switch of the cells in the same column p are controlled by the same signals Y p and Y p .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |