Patent US4654708A successfully refreshed from Google Patents.
US4654708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital video sync detection
Assignee: Racal Data Communications Inc
•
Filing: 1983-06-20
•
Granted: 1987-03-31
•
Expires: 2003-06-20
Abstract
Abstract An all digital video synchronization technique wherein a microprocessor tracks the incoming video signal and synchronizes its operation by stopping at a certain point in the sync signal and restarting upon occurrence of a horizontal sync pulse.
Inventors
- 👤 Mario de la Guardia
- 👤 Ming-Luh Kao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:33
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/10; H04N5/12
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
82 words
A method of synchronizing sampling in a video processor including a programmable microprocessor, said microprocessor being driven by a clock, comprising the steps of: stopping the clock to said microprocessor prior to an occurrence of a horizontal sync pulse in order to halt all instruction execution by said microprocessor, starting said clock upon the occurrence of said horizontal sync pulse in order to restart the instruction execution by said microprocessor, and sampling a video signal during times when said clock is running.
Claim 2
Independent Claim
82 words
A method of synchronizing sampling in a video processor including a programmable microprocessor, said microprocessor being driven by a clock, comprising the steps of: stopping the clock to said microprocessor prior to an occurrence of a horizontal sync pulse in order to halt all instruction execution by said microprocessor, starting said clock upon the occurrence of said horizontal sync pulse in order to restart the instruction execution by said microprocessor, and sampling a video signal during times when said clock is running.
Claim 3
Dependent Claim
43 words
The method of claim 1 wherein said starting step further comprises the steps of detecting a first transition to blacker-than-black of said horizontal sync pulse and starting said clock upon said detection of the first transition to blacker-than-black of said horizontal sync pulse.
Claim 4
Independent Claim
112 words
A method of synchronizing operation of a programmed digital video processor to a video sync signal, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of said video sync signal which fall below a selected threshold; stopping the clock to said microprocessor prior to an occurrence of a horizontal sync pulse in said pulse train in order to halt all instruction execution by said microprocessor; and starting said clock upon an occurrence of a transition in said pulse train corresponding to the occurrence of said horizontal sync pulse in order to restart the instruction execution by said microprocessor.
Claim 5
Independent Claim
112 words
A method of synchronizing operation of a programmed digital video processor to a video sync signal, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of said video sync signal which fall below a selected threshold; stopping the clock to said microprocessor prior to an occurrence of a horizontal sync pulse in said pulse train in order to halt all instruction execution by said microprocessor; and starting said clock upon an occurrence of a transition in said pulse train corresponding to the occurrence of said horizontal sync pulse in order to restart the instruction execution by said microprocessor.
Claim 6
Dependent Claim
41 words
The method of claim 3 further comprising the steps of: tracking, in the programmed digital video processor, said pulse train by testing for a presence of a predetermined signal pattern in said pulse train prior to the stopping of said clock.
Claim 7
Independent Claim
196 words
A method of synchronizing operation of a programmed digital video processor, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of a video sync signal which fall below a selected threshold; assigning logic levels to the pulses in said pulse train; detecting a vertical sync pattern in the pulse train by testing said logical levels, said vertical sync pattern having a last pulse; detecting occurrence of the last pulse in said vertical sync pattern; timing an interval approximately equal to an interval between the last pulse and a first horizontal sync pulse following said last pulse; detecting a signal transition in said first horizontal sync pulse; stopping the clock to said microprocessor, thereby halting all instruction execution by said microprocessor after the timing of said interval and restarting the clock to said microprocessor in coincidence with said detection of said signal transition in order to restart instruction execution by said microprocessor; and wherein prior to the stopping of said clock, a processor register is set and wherein said set processor register serves as a line counter for subsequent storage of video data.
Claim 8
Independent Claim
196 words
A method of synchronizing operation of a programmed digital video processor, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of a video sync signal which fall below a selected threshold; assigning logic levels to the pulses in said pulse train; detecting a vertical sync pattern in the pulse train by testing said logical levels, said vertical sync pattern having a last pulse; detecting occurrence of the last pulse in said vertical sync pattern; timing an interval approximately equal to an interval between the last pulse and a first horizontal sync pulse following said last pulse; detecting a signal transition in said first horizontal sync pulse; stopping the clock to said microprocessor, thereby halting all instruction execution by said microprocessor after the timing of said interval and restarting the clock to said microprocessor in coincidence with said detection of said signal transition in order to restart instruction execution by said microprocessor; and wherein prior to the stopping of said clock, a processor register is set and wherein said set processor register serves as a line counter for subsequent storage of video data.
Claim 9
Dependent Claim
32 words
The method of claim 5 further comprising prior to the detecting of said vertical sync pattern, a step of detecting a second horizontal sync pulse or detecting an equalizing pulse is performed.
Claim 10
Dependent Claim
33 words
The method of claim 5 wherein, said set processor register serves as a line counter and, after performing a step of storing a line of the video data, said processor register is decremented.
Claim 11
Dependent Claim
91 words
Apparatus for processing a video signal comprising: a processor means including a microprocessor; clock means for clocking said microprocessor and having a first input triggerable to stop said clocking of said microprocessor in order to halt all instruction execution by said microprocessor and a second input triggerable to restart said clocking in order to restart the instruction execution by said microprocessor; a sync separator means for producing a pulse train from sync levels of said video signal and supplying said pulse train to said second input and to said processor means.
Claim 12
Dependent Claim
91 words
Apparatus for processing a video signal comprising: a processor means including a microprocessor; clock means for clocking said microprocessor and having a first input triggerable to stop said clocking of said microprocessor in order to halt all instruction execution by said microprocessor and a second input triggerable to restart said clocking in order to restart the instruction execution by said microprocessor; a sync separator means for producing a pulse train from sync levels of said video signal and supplying said pulse train to said second input and to said processor means.
Claim 13
Dependent Claim
35 words
The apparatus of claim 8 wherein said processor means has a control lead connected to said first input and provides a control signal which stops said clock means at selected times during said pulse train.
Claim 14
Dependent Claim
165 words
A slow scan video processing system, comprising: input means for receiving an analog video signal; an A/D converter, coupled to said input means, for converting said analog video signal to a digital video signal; a frame store coupled to said A/D converter for receiving and storing a frame of said digital video signal; a sync separator coupled to said input for detecting a horizontal sync signal in said analog video signal; a control processor including a microprocessor coupled to said frame store for controlling said frame store; a clock coupled to said microprocessor for providing a clock signal to said computer; means responsive to an output of said control processor for stopping said clock signal to said microprocessor prior to the detection of said horizontal sync signal in order to halt all instruction execution by said microprocessor; and means for restarting said clock signal to said microprocessor upon the detection of said horizontal sync signal in order to restart the instruction execution by said microprocessor.
Claim 15
Dependent Claim
165 words
A slow scan video processing system, comprising: input means for receiving an analog video signal; an A/D converter, coupled to said input means, for converting said analog video signal to a digital video signal; a frame store coupled to said A/D converter for receiving and storing a frame of said digital video signal; a sync separator coupled to said input for detecting a horizontal sync signal in said analog video signal; a control processor including a microprocessor coupled to said frame store for controlling said frame store; a clock coupled to said microprocessor for providing a clock signal to said computer; means responsive to an output of said control processor for stopping said clock signal to said microprocessor prior to the detection of said horizontal sync signal in order to halt all instruction execution by said microprocessor; and means for restarting said clock signal to said microprocessor upon the detection of said horizontal sync signal in order to restart the instruction execution by said microprocessor.
Claim 16
Independent Claim
167 words
A method of synchronizing operation of a programmed digital video processor to a video sync signal, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of said video sync signal which fall below a selected threshold; stopping the clock to said microprocessor prior to occurrence of a horizontal sync pulse in said pulse train in order to halt all instruction execution by said microprocessor; starting said clock upon occurrence of a transition in said pulse train corresponding to the occurrence of said horizontal sync pulse in order to start the instruction execution by said microprocessor; detecting the presence of a vertical sync pulse pattern in said pulse train by testing for the presence of a predetermined signal pattern in said pulse train prior to stopping said clock; and detecting the occurrence of said transition in said horizontal sync pulse only after the step of detecting the presence of a vertical sync pulse pattern.
Claim 17
Independent Claim
167 words
A method of synchronizing operation of a programmed digital video processor to a video sync signal, said programmed digital video processor including a microprocessor being driven by a clock, comprising the steps of: generating a pulse train comprising pulses of said video sync signal which fall below a selected threshold; stopping the clock to said microprocessor prior to occurrence of a horizontal sync pulse in said pulse train in order to halt all instruction execution by said microprocessor; starting said clock upon occurrence of a transition in said pulse train corresponding to the occurrence of said horizontal sync pulse in order to start the instruction execution by said microprocessor; detecting the presence of a vertical sync pulse pattern in said pulse train by testing for the presence of a predetermined signal pattern in said pulse train prior to stopping said clock; and detecting the occurrence of said transition in said horizontal sync pulse only after the step of detecting the presence of a vertical sync pulse pattern.
Claim 18
Dependent Claim
149 words
Apparatus for processing an analog video signal comprising: a processor means including a microprocessor; clock means for clocking said microprocessor and having a first input triggerable to stop said clocking of said microprocessor in order to halt all instruction execution by the microprocessor and a second input triggerable to restart said clocking in order to restart the instruction by the microprocessor; a sync separator means for producing a pulse train from sync levels of said video signal and supplying said pulse train to said second input and to said processor means; said processor means including a control lead connected to said first input for providing a control signal which stops said clock means at selected times during said pulse train; means for converting said video signal to a digital signal; and a frame store controlled by said control processor to store digital video information contained in said digital signal.
Claim 19
Dependent Claim
149 words
Apparatus for processing an analog video signal comprising: a processor means including a microprocessor; clock means for clocking said microprocessor and having a first input triggerable to stop said clocking of said microprocessor in order to halt all instruction execution by the microprocessor and a second input triggerable to restart said clocking in order to restart the instruction by the microprocessor; a sync separator means for producing a pulse train from sync levels of said video signal and supplying said pulse train to said second input and to said processor means; said processor means including a control lead connected to said first input for providing a control signal which stops said clock means at selected times during said pulse train; means for converting said video signal to a digital signal; and a frame store controlled by said control processor to store digital video information contained in said digital signal.
References Cited (Backward Citations)
US4148070A
Cited
US4425581A
Cited
GB2105139A
Cited
US4464679A
Cited
US4599611A
Cited
US4568981A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |