US4654632A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter
Assignee: Mitsubishi Electric Corp
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Filing: 1985-05-10
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Granted: 1987-03-31
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Expires: 2005-05-10
Abstract
Abstract An A/D converter comprising a multiplexer for selecting one of multi-channel analog signals sequentially, an A/D converting circuit for converting a selected analog signal into digital data, a memory for storing converted data in certain address locations, and a control circuit operating on the multiplexer to select an input and addressing the memory in unison in response to an external trigger signal.
Inventors
- 👤 Koichi Yoshida
- 👤 Joji Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:42
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/05
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
187 words
An analog-to-digital converter with analog multiplexing and digital memory comprising: an analog multiplexer having a plurality of analog inputs, an analog output and input address means for selectively connecting one of the analog inputs to the analog output; an analog-to-digital converter having an analog input connected to the analog output of the multiplexer and having digital outputs; a dual port digital memory including (a) data inputs connected to the digital outputs of the converter, (b) input address means for selecting a memory address for storing data from the data inputs, (c) data outputs connectable to a computer data bus, and (d) output address means operable by a computer for selecting a memory address from which data is presented on the data outputs; and control means including (a) a presettable down counter having outputs connected to the input address means of the multiplexer and the memory, (b) presetting means including an external trigger input for presetting the counter to a preset value, (c) clock input means for decrementing the counter, and (d) disablement means responsive to a zero count in the counter for preventing decrementation of the counter.
Claim 2
Dependent Claim
187 words
An analog-to-digital converter with analog multiplexing and digital memory comprising: an analog multiplexer having a plurality of analog inputs, an analog output and input address means for selectively connecting one of the analog inputs to the analog output; an analog-to-digital converter having an analog input connected to the analog output of the multiplexer and having digital outputs; a dual port digital memory including (a) data inputs connected to the digital outputs of the converter, (b) input address means for selecting a memory address for storing data from the data inputs, (c) data outputs connectable to a computer data bus, and (d) output address means operable by a computer for selecting a memory address from which data is presented on the data outputs; and control means including (a) a presettable down counter having outputs connected to the input address means of the multiplexer and the memory, (b) presetting means including an external trigger input for presetting the counter to a preset value, (c) clock input means for decrementing the counter, and (d) disablement means responsive to a zero count in the counter for preventing decrementation of the counter.
Claim 3
Dependent Claim
38 words
An analog-to-digital converter according to claim 1 further comprising an early arrival priority circuit for arbitrating the read operation for data stored in said dual-port memory and the writing operation for said digital data in said dual-port memory.
Claim 4
Dependent Claim
41 words
An analog-to-digital converter according to claim 1 further comprising a priority arbitration circuit which prevents said dual-port memory, while reading out data stored in one address location, from being overwritten in said one address location by data from the analog-to-digital converter.
Claim 5
Dependent Claim
28 words
An analog-to-digital converter according to claim 1, wherein said disablement means generates an interrupt request signal for a computer in response to a zero count in the counter.
References Cited (Backward Citations)
US4345323A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |