Digital phase meter apparatus

Claim 1

A digital phase meter apparatus for measuring phase difference comprising in combination: a first means for signal squaring to receive a clock signal, said first signal squaring means squaring said clock signal to provide a first clock signal, a second means for signal squaring to receive an input signal, said second signal squaring means squaring said input signal to provide a test signal, a third means for signal squaring to receive a reference signal, said third signal squaring means squaring said reference signal to provide a first reference signal, a means for leading edge/phase detection, said leading edge/phase detection means receiving said test signal and said first reference signal, said leading edge/phase detection means receiving a first and second control signal, said first control signal initiates the leading edge detection process, said second control signal starts the phase detection process, said leading edge/phase detection means providing an enable signal at the start of the phase detection process, said enable signal is activated for the entire time of the phase detection process, a means for counting bits, said bit counting means receiving said first clock signal from said signal squaring means, said bit counting means receiving said enable signal from said leading edge/phase detection means which enables said bit counting means and allows said first clock signal to drive said bit counting means, said first clock signal continues to increment said bit counting means for the duration of said enable signal, said bit counting means providing an n-bit output signal where n is a predetermined positive number, a first latch means operatively connected to said bit counting means to receive said n-bit output therefrom, said first latch means providing a first n-bit latch output signal to a data bus line, and, a second latch means operatively connected to said leading edge/phase detection means, said second latch means receiving a latch input signal from said leading edge/phase detection means, said second latch means providing a second n-bit latch output to said data bus line, said n-bit latch output signal including said latch input signal, said latch input signal on said data bus line signaling said third control signal, said third control signal activating said first latch means to read out said first n-bit latch output onto said data bus line, said first n-bit latch output signal comprising the phase difference between said input signal and said reference signal.