Patent US4653079A successfully refreshed from Google Patents.
US4653079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse doubler circuit with complementary pulse inputs
Assignee: NXP USA Inc
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Filing: 1986-01-28
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Granted: 1987-03-24
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Expires: 2006-01-28
Abstract
Abstract A circuit for producing a pair of output pulses for each cycle of differentially applied input pulses includes a pair of input transistors to which the differential input pulses are applied and a pair of output transistors the collectors of which are connected to an output of the pulse doubling circuit and the bases of which are respectively coupled to the emitters of a corresponding input transistor. A pair of delay circuits are provided coupled respectively from one of the input transistors to the base of the opposite output transistor. The output transistors are responsive to the respective input transistor being rendered conductive while the other input transistor is rendered non-conductive for causing the output voltage to change from a first level to a second level while the one delay circuit is responsive to the other input transistor turning off for turning the respective output transistor to turn off a predetermined time thereafter thereby causing the output voltage to change from the second level to the first level.
Inventors
- 👤 Gordon H. Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:42
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/00006; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00078; H03K2005/0015; H03K2005/00163
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
277 words
A pulse doubler circuit for producing a pair of pulses at an output thereof for each cycle of differentially applied input pulses, comprising: first and second input transistor circuit means which are differentially rendered conductive and non-conductive respectively in response to the input pulses; first and second output transistor circuit means coupled respectively to said first and second input transistor circuit means, said first output transistor circuit means being rendered conductive by said first input transistor circuit means being rendered conductive for causing the voltage at the output of the pulse doubler circuit to change from a first level to a second level, said second output transistor circuit means being rendered conductive in response to said second input transistor circuit means being rendered conductive for causing said voltage at the output of the pulse doubler circuit to change from said first level to said second level; and first and second delay circuit means, said first delay circuit means being responsive to said second input transistor circuit means being rendered non-conductive as said first input transistor circuit means is rendered conductive for causing said first output transistor circuit means to be turned off a predetermined time thereafter such that said voltage at the output of the circuit changes from said second level to said first level and said second delay circuit means being responsive to said first input transistor circuit means being rendered non-conductive as said second input transistor circuit means is rendered conductive for causing said second output transistor circuit means to turned off a predetermined time thereafter such that said voltage at the output of the circuit changes from said second level to said first level.
Claim 2
Dependent Claim
277 words
A pulse doubler circuit for producing a pair of pulses at an output thereof for each cycle of differentially applied input pulses, comprising: first and second input transistor circuit means which are differentially rendered conductive and non-conductive respectively in response to the input pulses; first and second output transistor circuit means coupled respectively to said first and second input transistor circuit means, said first output transistor circuit means being rendered conductive by said first input transistor circuit means being rendered conductive for causing the voltage at the output of the pulse doubler circuit to change from a first level to a second level, said second output transistor circuit means being rendered conductive in response to said second input transistor circuit means being rendered conductive for causing said voltage at the output of the pulse doubler circuit to change from said first level to said second level; and first and second delay circuit means, said first delay circuit means being responsive to said second input transistor circuit means being rendered non-conductive as said first input transistor circuit means is rendered conductive for causing said first output transistor circuit means to be turned off a predetermined time thereafter such that said voltage at the output of the circuit changes from said second level to said first level and said second delay circuit means being responsive to said first input transistor circuit means being rendered non-conductive as said second input transistor circuit means is rendered conductive for causing said second output transistor circuit means to turned off a predetermined time thereafter such that said voltage at the output of the circuit changes from said second level to said first level.
Claim 3
Dependent Claim
73 words
The pulse doubler circuit of claim 1 wherein said first input transistor circuit means includes a transistor having a base, collector and emitter, said base being coupled to a first input of the pulse doubler circuit, said collector being coupled both to a first power supply conductor to which an operating potential is supplied and to said second delay circuit means, and said emitter being coupled to said first transistor output circuit means.
Claim 4
Dependent Claim
135 words
The pulse doubler circuit of claim 2 wherein said first delay circuit means includes: a first transistor having a base, a collector and an emitter, said base being coupled to said second input transistor circuit means, said collector being coupled to said first power supply conductor; a second transistor having a base, a collector and an emitter, said base being coupled to said emitter of said first transistor of said first delay circuit means, said collector being coupled to said first power supply conductor; and a third transistor having a base, a collector and an emitter, said base being coupled to said emitter of said second transistor of said first delay circuit means, said collector being coupled to said first output transistor circuit means and said emitter being coupled to a second power supply conductor.
Claim 5
Dependent Claim
60 words
The pulse doubler circuit of claim 3 wherein said first delay circuit means includes: a first resistor coupled between said emitter and said base of said first and second transistors respectively of said first delay circuit means; and capacitive means coupled between said base of said second transistor of said first delay circuit means and said second power supply conductor.
Claim 6
Dependent Claim
44 words
The pulse doubler circuit of claim 4 wherein said capacitive means includes a transistor having a base coupled to said second power supply conductor, an emitter and a collector each connected to said base of said second transistor of said first delay circuit means.
Claim 7
Dependent Claim
55 words
The pulse doubler circuit of claim 5 wherein said first output transistor circuit means is a transistor having a base coupled to the collector of said third transistor of said first delay circuit means, a collector coupled to the output of the pulse doubler circuit and an emitter coupled to said second power supply conductor.
Claim 8
Dependent Claim
66 words
The pulse doubler circuit of claim 6 wherein said second input transistor circuit means includes a transistor having a base, collector and emitter, said base being coupled to a second input of the pulse doubler circuit, said collector being coupled both to said first power supply conductor and to said first delay circuit means, and said emitter being coupled to said second transistor output circuit means.
Claim 9
Dependent Claim
135 words
The pulse doubler circuit of claim 7 wherein said second delay circuit means includes: a first transistor having a base, a collector and an emitter, said base being coupled to said first input transistor circuit means, said collector being coupled to said first power supply conductor; a second transistor having a base, a collector and an emitter, said base being coupled to said emitter of said first transistor of said second delay circuit means, said collector being coupled to said first power supply conductor; and a third transistor having a base, a collector and an emitter, said base being coupled to said emitter of said second transistor of said second delay circuit means, said collector being coupled to said second output transistor circuit means and said emitter being coupled to said second power supply conductor.
Claim 10
Dependent Claim
60 words
The pulse doubler circuit of claim 8 wherein said second delay circuit means includes: a first resistor coupled between said emitter and said base of said first and second transistors respectively of said second delay circuit means; and capacitive means coupled between said base of said second transistor of said second delay circuit means and said second power supply conductor.
Claim 11
Dependent Claim
44 words
The pulse doubler circuit of claim 9 wherein said capacitive means includes a transistor having a base coupled to said second power supply conductor, an emitter and a collector each connected to said base of said second transistor of said second delay circuit means.
Claim 12
Dependent Claim
55 words
The pulse doubler circuit of claim 10 wherein said second output transistor circuit means is a transistor having a base coupled to the collector of said third transistor of said second delay circuit means, a collector coupled to the output of the pulse doubler circuit and an emitter coupled to said second power supply conductor.
References Cited (Backward Citations)
US3555258A
Cited
US3562673A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |