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Frequency hopping data communication system

Assignee: ITT Inc
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Filing: 1984-10-19
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Granted: 1987-03-24
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Expires: 2004-10-19
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Abstract

Abstract A frequency hopping data communication system for a bidirectional communication system is described in which improved operation in a jamming and/or fading environment is provided. A pseudo-noise code generator is utilized to provide a random sequence of ON-OFF pulses representative of binary numbers which cause a microprocessor to select data at a desired frequency which is then coupled to a frequency synthesizer to provide a controllable frequency and an improved anti-jam capability in both a receiver and transmitter.

Inventors

  • 👤 Joseph Kadin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 05:46
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/713; H04B1/7156; H04B2001/71563

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 365 words
A frequency hopping data communication system comprising: first means to provide a predetermined random sequence of different frequencies; second means coupled to said first means, said second means being responsive to binary data to transmit at least one of said different frequencies of said random sequences of frequencies upon each occurrence of one binary condition of said binary data and to block transmission of said random sequence of frequencies upon each occurrence of the other binary condition of said binary data; third means to provide a predetermined random sequence of numbers representing said different frequencies of said random sequence of frequencies; fourth means coupled to said second means and said third means responsive to said random sequence of numbers to recover said binary data; and fifth means coupled to said third means and said fourth means to synchronize said third means to said second means; wherein said first means includes a first pseudo-noise code generator coupled to a first clock to produce a first random bit stream, a first microprocessor coupled to said first code generator responding to successive portions of said first random bit stream to provide first output signals representing number corresponding to said different frequencies of said random sequence of frequencies, and a frequency synthesizer coupled to said first microprocessor responsive to said first output signals to provide said random sequence of frequencies and wherein said fourth means includes a wide band agile filter coupled to said second microprocessor to recover signals having said different frequencies of said random sequence of frequencies, amplitude measuring means coupled to said agile filter and said second microprocessor to provide a control signal proportional to the amplitude of said recovered signals for said second microprocessor, and threshold circuit means coupled to said amplitude measuring means, said acquisition circuit and said second microprocessor, said threshold circuit means having two spaced amplitude threshold levels adjusted by said second microprocessor in accordance with said amplitude control signal and the expected one of said different frequencies of said random sequence of frequencies to recover said binary data when individual ones of said different frequencies of said random sequence of frequencies have an amplitude non-coincidentally present between said two threshold levels.
Claim 2
Dependent Claim 365 words
A frequency hopping data communication system comprising: first means to provide a predetermined random sequence of different frequencies; second means coupled to said first means, said second means being responsive to binary data to transmit at least one of said different frequencies of said random sequences of frequencies upon each occurrence of one binary condition of said binary data and to block transmission of said random sequence of frequencies upon each occurrence of the other binary condition of said binary data; third means to provide a predetermined random sequence of numbers representing said different frequencies of said random sequence of frequencies; fourth means coupled to said second means and said third means responsive to said random sequence of numbers to recover said binary data; and fifth means coupled to said third means and said fourth means to synchronize said third means to said second means; wherein said first means includes a first pseudo-noise code generator coupled to a first clock to produce a first random bit stream, a first microprocessor coupled to said first code generator responding to successive portions of said first random bit stream to provide first output signals representing number corresponding to said different frequencies of said random sequence of frequencies, and a frequency synthesizer coupled to said first microprocessor responsive to said first output signals to provide said random sequence of frequencies and wherein said fourth means includes a wide band agile filter coupled to said second microprocessor to recover signals having said different frequencies of said random sequence of frequencies, amplitude measuring means coupled to said agile filter and said second microprocessor to provide a control signal proportional to the amplitude of said recovered signals for said second microprocessor, and threshold circuit means coupled to said amplitude measuring means, said acquisition circuit and said second microprocessor, said threshold circuit means having two spaced amplitude threshold levels adjusted by said second microprocessor in accordance with said amplitude control signal and the expected one of said different frequencies of said random sequence of frequencies to recover said binary data when individual ones of said different frequencies of said random sequence of frequencies have an amplitude non-coincidentally present between said two threshold levels.
Claim 3
Dependent Claim 52 words
A system according to claim 1, wherein said second means includes switching means coupled to said frequency synthesizer to transmit said one of said different frequencies upon each occurence of said one binary condition and to block transmission of said random sequence of frequencies upon each occurence of said other binary condition.
Claim 4
Dependent Claim 58 words
A system according to claim 2, wherein said fifth means includes a second clock, and a synchronization acquisition circuit coupled to said second clock, said fourth means and said second code generator responsive to said recovered binary data to slip the timing of said second bit stream to synchronize said second bit stream with said recovered binary data.
Claim 5
Dependent Claim 164 words
A frequency hopping data transmitter comprising: first means to provide a predetermined random sequence of different frequencies; and second means coupled to said first means, said second means being responsive to binary data to transmit at least one of said different frequencies of said random sequence of frequencies upon each occurrence of one binary condition of said binary data and to block transmission of said random sequence of frequencies upon each occurrence of the other binary condition of said binary data, to provide ON-OFF keying of said random sequence of frequencies; and wherein said first means includes a pseudo-noise code generator coupled to a clock to produce a random bit stream, a microprocessor coupled to said code generator responding to successive portions of said random bit stream to provide output signals representing numbers corresponding to said different frequencies of said random sequence of frequencies, and a frequency sythesizer coupled to said microprocessor responsive to said output signals to provide said random sequence of frequencies.
Claim 6
Dependent Claim 164 words
A frequency hopping data transmitter comprising: first means to provide a predetermined random sequence of different frequencies; and second means coupled to said first means, said second means being responsive to binary data to transmit at least one of said different frequencies of said random sequence of frequencies upon each occurrence of one binary condition of said binary data and to block transmission of said random sequence of frequencies upon each occurrence of the other binary condition of said binary data, to provide ON-OFF keying of said random sequence of frequencies; and wherein said first means includes a pseudo-noise code generator coupled to a clock to produce a random bit stream, a microprocessor coupled to said code generator responding to successive portions of said random bit stream to provide output signals representing numbers corresponding to said different frequencies of said random sequence of frequencies, and a frequency sythesizer coupled to said microprocessor responsive to said output signals to provide said random sequence of frequencies.
Claim 7
Dependent Claim 78 words
A transmitter acording to claim 4, wherein said first means includes a pseudo-noise code generator coupled to a clock to produce a random bit stream, a microprocessor coupled to said code generator responding to successive portions of said random bit stream to provide output signals representing numbers corresponding to said different frequencies of said random sequence of frequencies, and a frequency sythesizer coupled to said microprocessor responsive to said output signals to provide said random sequence of frequencies.
Claim 8
Dependent Claim 58 words
A transmitter according to claim 4, wherein said second means includes switching means coupled to said frequency synthesizes to transmit said one of said different frequencies of said random sequence of frequencies upon each occurrence of said one binary condition and to block transmission of said random sequence of frequencies upon each occurence of said other binary condition.
Claim 9
Dependent Claim 187 words
A frequency hopping data receiver to recover binary data transmitted by the presences of at least one different frequency of a random sequence of different frequencies representing one binary condition and by the absence of said random sequence of different frequencies representing the other binary condition in which said random sequence of frequencies is keyed ON and OFF, comprising: first means to provide a predetermined random sequence of number representing said different frequencies of said random sequence of frequencies; second means receiving said transmitted binary data and coupled to said first means, said second means being responsive to said random sequence of numbers to recover said binary data; and third means coupled to said first means and said second means to synchronize said first means to said random sequence of frequencies and wherein said first means includes a pseudo-noise code generator coupled to said third means to produce a random bit stream in synchronism with said random sequence of frequencies, and a microprocessor coupled to said code generator responding to successive portions of said random bit stream to provide output signals representing said random sequence of numbers.
Claim 10
Dependent Claim 187 words
A frequency hopping data receiver to recover binary data transmitted by the presences of at least one different frequency of a random sequence of different frequencies representing one binary condition and by the absence of said random sequence of different frequencies representing the other binary condition in which said random sequence of frequencies is keyed ON and OFF, comprising: first means to provide a predetermined random sequence of number representing said different frequencies of said random sequence of frequencies; second means receiving said transmitted binary data and coupled to said first means, said second means being responsive to said random sequence of numbers to recover said binary data; and third means coupled to said first means and said second means to synchronize said first means to said random sequence of frequencies and wherein said first means includes a pseudo-noise code generator coupled to said third means to produce a random bit stream in synchronism with said random sequence of frequencies, and a microprocessor coupled to said code generator responding to successive portions of said random bit stream to provide output signals representing said random sequence of numbers.
Claim 11
Dependent Claim 56 words
A receiver according to claim 7, wherein said third means includes a clock, and a synchronization acquisition circuit coupled to said clock, said second means and said code generator responsive to said recovered binary data to slip the timing of said random bit stream to synchronize said random bit stream with said random sequence of frequencies.
Claim 12
Dependent Claim 138 words
A receiver according to claim 8, wherein said second means includes a wide band agile filter coupled to said microprocessor to recover signals having said different frequencies of said random sequence of frequencies, amplitude measuring means coupled to said agile filter and said microprocessor to provide a control signal proportional to the amplitude of said recovered signals for said microprocessor, and threshold circuit means coupled to said amplitude measuring means, said acquisition circuit and said microprocessor, said threshold circuit means having two spaced amplitude threshold levels adjusted by said microprocessor in accordance with said amplitude control signal and the expected one of said different frequencies of said random sequence of frequencies to recover said binary data when individual ones of said different frequencies of said random sequence of frequencies have an amplitude non-coincidentally between said two threshold levels.

References Cited (Backward Citations)

US3878527A Cited
US3980945A Cited
US4355399A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-03-23 1990-09-22 1991-03-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-03-23 1994-09-22 1995-03-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-03-23 1998-09-22 1999-03-24 $7700.00 Window Closed / Lapsed

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