Random access memory with high density and low power

Claim 1

A semiconductor memory comprising: a plurality of memory cells each of which is comprised of: a first n-channel MOST and a second n-channel MOST, each of which is provided in a p-type semiconductor body, the gate of said first n-channel MOST being connected to the drain of said second n-channel type MOST, and the gate of said second n-channel type MOST being connected to the drain of said first n-channel type MOST; and a first p-channel MOST and a second p-channel MOST, each of which is provided in an n-type semiconductor body, the drain of said first p-channel MOST being coupled to the drain of said first n-channel MOST to constitute a first storage node, and the drain of said second p-channel MOST being coupled to the drain of said second n-channel MOST to constitute a second storage node; a plurality of first and second data lines each of which is coupled to the source of the first and second p-channel MOSTs in the memory cells; a plurality of word lines coupled to the gates of the first and second p-channel MOSTs in the memory cells; a first terminal region provided in said n-type body and coupled to a first power source terminal so as to bias said drains of the p-channel MOSTs in reverse and supply a current in reverse bias ILp to said drains of the p-channel MOSTs; and a second terminal region provided in said p-type body and coupled to a second power source terminal so as to bias said drains of the n-channel MOSTs in reverse, wherein said current in reverse bias ILp is greater than a current in reverse bias ILn that flows from said drains of the n-channel MOSTs into said second terminal region.