Patent US4652991A successfully refreshed from Google Patents.
US4652991A
Expired / Lapsed
US
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Data transfer apparatus
Assignee: NEC Corp
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Filing: 1985-10-23
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Granted: 1987-03-24
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Expires: 2005-10-23
Abstract
Abstract In an information processing apparatus of the type comprising a CPU, a memory device and input and output device, where a portion of the memory region storing a plurality of bytes as a unit of data to be stored overlaps a portion of the memory region to which the data are transferred, there are provided an address difference calculating circuit for calculating the difference of the addresses at the data transfer and data receiving sides, a comparator for comparing respective addresses, and a recurrent data pattern forming circuit for exchanging data between the memory region for storing the data and the memory region for receiving the data by a number corresponding to the difference of the addresses.
Inventors
- 👤 Kozo Yamano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F12/00; G06F12/02; G06F12/04
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
534 words
A data transfer apparatus having a memory device, which memory device has a first memory region for storing a plurality of bytes of data to be transferred to a second memory region, which second memory region overlaps a portion of said first memory region, said data transfer apparatus comprising: (a) a transfer originating side address storing means which addresses said memory device for storing the address of one of said plurality of bytes of data stored in said first memory region; (b) a transfer receiving side address storing means which addresses said memory device for storing the address of one of a plurality of bytes located in said second memory region; (c) address difference calculating means for calculating the differences between addresses stored in said transfer originating side address storing means and said transfer receiving side address storing means; (d) comparing means for comparing addresses stored in said transfer originating side address storing means and said transfer receiving side address storing means and generating a control signal when the transfer originating side address storing means and the transfer receiving side address storing means address the same relative byte position within respective data words stored in said memory device; (e) read out means coupled to said comparing means for reading said plurality of bytes stored in said first memory region; (f) transfer originating side data storing means coupled to said memory device for storing said plurality of bytes of data read by said read out means; (g) transfer receiving side data storing means coupled to said memory device for storing data at said address located in said second memory region; (h) recurrent data pattern forming means coupled to said transfer receiving side data storing means and said transfer originating side data storing means for forming a recurrent data pattern of the data stored in said transfer originating side data storing means and said transfer receiving side data storing means and storing said recurrent data pattern in said transfer originating side data storing means; (i) byte selection means for receiving the address of a byte stored in said transfer originating side address storing means and for receiving the address of a byte stored in said transfer receiving side address storing means, which addresses are determined by the least significant two bits of said transfer originating side addreass storing means and said transfer receiving side address storing means respectively, and which addresses are used to respectively select a byte position in the transfer originating side data storing means and a byte position in the transfer receiving side data storing means, said selected byte positions for storing data from said transfer originating side data storing means to said transfer receiving side data storing means; (j) repeat means coupled to said address difference calculating means, said read out means, said byte designation means, and said transfer originating side data storing means for repeating the operations performed by said byte selection means, said transfer originating side data storing means, and said readout means a number of times equal to the address difference calculated by said address difference calculating means; and (k) transfer means for transferring the data formed by said recurrent data pattern forming means to said second memory region.
Claim 2
Dependent Claim
534 words
A data transfer apparatus having a memory device, which memory device has a first memory region for storing a plurality of bytes of data to be transferred to a second memory region, which second memory region overlaps a portion of said first memory region, said data transfer apparatus comprising: (a) a transfer originating side address storing means which addresses said memory device for storing the address of one of said plurality of bytes of data stored in said first memory region; (b) a transfer receiving side address storing means which addresses said memory device for storing the address of one of a plurality of bytes located in said second memory region; (c) address difference calculating means for calculating the differences between addresses stored in said transfer originating side address storing means and said transfer receiving side address storing means; (d) comparing means for comparing addresses stored in said transfer originating side address storing means and said transfer receiving side address storing means and generating a control signal when the transfer originating side address storing means and the transfer receiving side address storing means address the same relative byte position within respective data words stored in said memory device; (e) read out means coupled to said comparing means for reading said plurality of bytes stored in said first memory region; (f) transfer originating side data storing means coupled to said memory device for storing said plurality of bytes of data read by said read out means; (g) transfer receiving side data storing means coupled to said memory device for storing data at said address located in said second memory region; (h) recurrent data pattern forming means coupled to said transfer receiving side data storing means and said transfer originating side data storing means for forming a recurrent data pattern of the data stored in said transfer originating side data storing means and said transfer receiving side data storing means and storing said recurrent data pattern in said transfer originating side data storing means; (i) byte selection means for receiving the address of a byte stored in said transfer originating side address storing means and for receiving the address of a byte stored in said transfer receiving side address storing means, which addresses are determined by the least significant two bits of said transfer originating side addreass storing means and said transfer receiving side address storing means respectively, and which addresses are used to respectively select a byte position in the transfer originating side data storing means and a byte position in the transfer receiving side data storing means, said selected byte positions for storing data from said transfer originating side data storing means to said transfer receiving side data storing means; (j) repeat means coupled to said address difference calculating means, said read out means, said byte designation means, and said transfer originating side data storing means for repeating the operations performed by said byte selection means, said transfer originating side data storing means, and said readout means a number of times equal to the address difference calculated by said address difference calculating means; and (k) transfer means for transferring the data formed by said recurrent data pattern forming means to said second memory region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |